Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

Abstract: Provided is a display substrate, including: a substrate; a plurality of pixels disposed on a side of the substrate, each of the pixels including a pixel circuit and a light-emitting element; and at least one second power line and a plurality of repair lines that are disposed on a side of the substrate. The pixel circuit is configured to transmit a drive signal to the first electrode of the light-emitting element, and the light-emitting element is configured to emit light based on the drive signal and a first power signal supplied by the first power line. The second power line is coupled to the repair line. The second power line is configured to transmit a second power signal to the first electrode of the coupled light-emitting element by the repair line. A potential of the second power signal is greater than a potential of the first power signal.

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

Abstract: A texture recognition apparatus and an opposite substrate are provided. The texture recognition apparatus includes a light source array, an image sensor array and a light shielding layer. The light source array includes a plurality of light sources; the image sensor array includes a plurality of image sensors, an orthographic projection of the light shielding layer on a plane where the light source array is located is between two adjacent light sources, an orthographic projection of the light shielding layer on a plane where the image sensor array is located at least partially overlaps with the plurality of image sensors; the light shielding layer has at least one opening, and at least a part of an orthographic projection of the first opening on the plane where the image sensor array is located is at least on one side of the first image sensor or overlaps with the first image sensor.

Abstract: A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Abstract: A solid-state sodium-carbon dioxide battery is provided. The solid-state sodium-carbon dioxide battery comprises a positive electrode, a negative electrode, and an inorganic solid-state electrolyte disposed between the positive electrode and the negative electrode, wherein the positive electrode can catalyze the reaction of sodium ions and carbon dioxide, the negative electrode comprises sodium.

Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

Abstract: The invention discloses a blockchain-based intrusion detection system for railway signal, which is built on a blockchain's distributed chain structure, without a central, trusted control center. This design mitigates the vulnerabilities associated with centralized intrusion detection centers. Additionally, by utilizing a blockchain-based distributed structure, it also eliminates the risk of a single point of failure for the intrusion detection center. Moreover, the data within the blockchain-based intrusion detection system is highly resistant to malicious tampering. This is achieved by leveraging the consensus mechanism inherent in the blockchain, which can achieve consensus among intrusion detection nodes. The current invention solves the internal evil attacks and avoid the inability to reach consensus between nodes due to internal evil, thereby affecting the intrusion detection performance; at the same time, the intrusion detection model can resist external network attacks.

Abstract: It has been discovered that overexpression of DLC1-i1 partly rescues neuronal formation and apoptosis of neuromuscular cells in subjects with spinal muscular atrophy (SMA). Since loss of DLC1-i1 confers specific MN defects in SMA, compositions and methods thereof for the treatment of SMA by delivery of AAV-SYN-DLC1-i1 into the neuronal population of subject with SMA are provided. The methods improve survival and restore locomotion ability to a greater extent than that of commercially-available compositions and methods. Methods including administration of both DLC1-i1 and SMN1 transgenes provide synergistic effects in improving the survival and enhancing locomotion ability in subject with SMA.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 ?m to 30 ?m; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

Abstract: A composition for forming a release coating comprises (A) an organopolysiloxane having an average of at least two carbinol functional groups per molecule. The organopolysiloxane (A) is present in the composition in an amount of from 50 to 99 wt. % based on the total weight of the composition. The composition further comprises (B) a polyisocyanate. The release coating formed with the composition is not a foam. A release coating formed with the composition is also disclosed. In addition, a method of preparing a coated substrate comprising a release coating disposed on a substrate, as well as the coated substrate formed in accordance with the method, are disclosed.

Abstract: The present invention discloses an image processing method. The image processing method includes the following steps: (a), a to-be-processed image is corrected as a first correction image according to a first mapping relationship along a correction direction; (b) the first correction image by an angle is rotated; and (c) the rotated first correction image is corrected as a second correction image according to a second mapping relationship along the same correction direction. In embodiment, given that the to-be-processed image is deformed along two different directions, the to-be-processed image is corrected along the same correction direction, such that correction complexity could be reduced.

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.