Patents by Inventor Shi-Ning Yang
Shi-Ning Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200295025Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.Type: ApplicationFiled: March 17, 2020Publication date: September 17, 2020Inventors: Zhenyu LU, Simon Shi-Ning YANG, Feng PAN, Steve Weiyi YANG, Jun CHEN, Guanping WU, Wenguang SHI, Weihua CHENG
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Publication number: 20200265913Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Jong Jun KIM, Feng PAN, Jong Seuk LEE, Zhenyu LU, Yongna LI, Lidong SONG, Youn Cheul KIM, Steve Weiyi YANG, Simon Shi-Ning YANG
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Publication number: 20200203285Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: December 31, 2019Publication date: June 25, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Patent number: 10679721Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.Type: GrantFiled: July 26, 2018Date of Patent: June 9, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
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Patent number: 10593690Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.Type: GrantFiled: July 26, 2018Date of Patent: March 17, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Simon Shi-Ning Yang, Feng Pan, Steve Weiyi Yang, Jun Chen, Guanping Wu, Wenguang Shi, Weihua Cheng
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Patent number: 10522474Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: GrantFiled: July 26, 2018Date of Patent: December 31, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Xiaowang Dai, Dan Liu, Steve Weiyi Yang, Simon Shi-Ning Yang
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Patent number: 10423176Abstract: A low-dropout regulator comprises a first switching transistor, a comparator, and a Miller capacitor. The first terminal of the first switching transistor is connected to a load, and the second terminal of the first switching transistor is connected to a power supply voltage. The first input terminal of the comparator is connected to a reference voltage, the second input terminal of the comparator is connected to the first terminal of the first switching transistor, and the output terminal of the comparator is connected to the control terminal of the first switching transistor. The first terminal of the Miller capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the Miller capacitor is connected to the first terminal of the first switching transistor and the load.Type: GrantFiled: July 26, 2018Date of Patent: September 24, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Feng Pan, Zhenyu Lu, Steve Weiyi Yang, Simon Shi-Ning Yang
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Publication number: 20190244893Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng ZHU, Zhenyu LU, Jun CHEN, Yushi HU, Qian TAO, Simon Shi-Ning YANG, Steve Weiyi YANG
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Publication number: 20190244892Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate, The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20190164983Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: ApplicationFiled: December 3, 2018Publication date: May 30, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi HU, Zhenyu LU, Qian TAO, Jun CHEN, Simon Shi-Ning YANG, Steve Weiyi YANG
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Patent number: 10283452Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: March 23, 2018Date of Patent: May 7, 2019Assignee: Yangtze Memory Technology Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Wiyi Yang
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Publication number: 20190088589Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: ApplicationFiled: March 23, 2018Publication date: March 21, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng ZHU, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Wiyi Yang
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Publication number: 20190081069Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: ApplicationFiled: July 27, 2018Publication date: March 14, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20190064862Abstract: A low-dropout regulator comprises a first switching transistor, a comparator, and a Miller capacitor. The first terminal of the first switching transistor is connected to a load, and the second terminal of the first switching transistor is connected to a power supply voltage. The first input terminal of the comparator is connected to a reference voltage, the second input terminal of the comparator is connected to the first terminal of the first switching transistor, and the output terminal of the comparator is connected to the control terminal of the first switching transistor. The first terminal of the Miller capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the Miller capacitor is connected to the first terminal of the first switching transistor and the load.Type: ApplicationFiled: July 26, 2018Publication date: February 28, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Feng PAN, Zhenyu LU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Publication number: 20190057756Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.Type: ApplicationFiled: July 26, 2018Publication date: February 21, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
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Publication number: 20190057974Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.Type: ApplicationFiled: July 26, 2018Publication date: February 21, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Simon Shi-Ning YANG, Feng PAN, Steve Weiyi YANG, Jun CHEN, Guanping WU, Wenguang SHI, Weihua CHENG
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Publication number: 20190051610Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: July 26, 2018Publication date: February 14, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Patent number: 10147732Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: GrantFiled: March 23, 2018Date of Patent: December 4, 2018Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
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Publication number: 20140089845Abstract: An apparatus capable of switching displayed pictures in response to a slide gesture by a user includes a display screen for displaying a zoomed in current picture, a touch determining unit, a picture processing unit, a control unit, a time calculating unit, and a calculating unit. The picture processing unit determines a width value of the current picture and a distance between a side of the current picture and an edge of the display screen adjacent to the side. The control unit controls the display screen to only display the target picture if a ratio of the distance to the width is equal to or greater than a predetermined ratio, and controls the display screen to only redisplay the current picture if a time duration of a slide gesture from beginning to ending is smaller than a predetermined time period. A related method is also provided.Type: ApplicationFiled: January 5, 2013Publication date: March 27, 2014Inventors: HAI-SEN LIANG, CHIH-SAN CHIANG, SHI-NING YANG, XIANG HE, HUA-DONG CHENG
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Patent number: 7442637Abstract: A method for processing IC designs for different metal BEOL processes is provided for enabling fabricating using a metal fabrication process an IC originally having a backend design for a different metal fabrication process. The method first determines layer constructions of an original design of an IC for a first metal backend process, and, based on the layer constructions of the original design of the IC, constructs primitive layer constructions of a target design of the IC for a second metal backend process. The method then tunes an effective dielectric constant of a dielectric layer of the target design to match an associated capacitance of the target backend design with a corresponding capacitance of the original backend design. The method can be used to convert a backend design of an IC from an old metal process (such as Al process) to a new metal process (such as Cu process), without redesigning the IC for the new metal BEOL fabrication process.Type: GrantFiled: August 15, 2005Date of Patent: October 28, 2008Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Jiannong Su, Simon Shi-ning Yang, Jian Zhang