Patents by Inventor Shi-Ning Yang

Shi-Ning Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design
    Patent number: 7381646
    Abstract: A semiconductor fabrication method or process is provided for fabricating an integrated circuit (IC) originally having an Al backend design using a Cu BEOL fabrication process. The method converts the Al backend design to a Cu backend design without redesigning the IC for Cu BEOL fabrication process, and uses the resultant Cu design to fabricate the IC using Cu BEOL fabrication process. The Al-Cu conversion first determines layer construction of the Al design, and then matches metal resistances of the Al design with metal resistances of a Cu design, matches intra-metal capacitances of the Al design with intra-metal capacitances of the Cu design, and matches inter-metal capacitance of the Al design with inter-metal capacitances of the Cu design.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: June 3, 2008
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jiannong Su, Simon Shi-ning Yang, Jian Zhang
  • Guard wall to reduce delamination effects within a semiconductor die
    Patent number: 5986315
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: November 16, 1999
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter
  • Via hole profile and method of fabrication
    Patent number: 5874358
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: February 23, 1999
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Anchored via connection
    Patent number: 5619071
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: April 8, 1997
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Via hole profile and method of fabrication
    Patent number: 5470790
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: November 28, 1995
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Method of forming a guard wall to reduce delamination effects
    Patent number: 5270256
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: December 14, 1993
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter