Patents by Inventor Shi Qi
Shi Qi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12061815Abstract: A method for locating a hard disk applied in a server which governs many hard disks including some making use of one HD slot by an expander customizes the SCSI Enclosure Services (SES) custom page of an expander of a JBOD device, and obtains and stores information of the JBOD device through the expander. The server further obtains information of a hard disk to be located, and obtains information of the JBOD device hosting the hard disk to be located according to the information of the hard disk to be located.Type: GrantFiled: November 10, 2022Date of Patent: August 13, 2024Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Jie Yuan, Shi-Qi Chen
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Patent number: 12051859Abstract: In certain embodiments, a system includes an optical switch matrix, an optical lens coupled to the switch matrix, and a wireless transmitter coupled to the lens. The switch matrix is configured to switch first optical signals from input ports to output ports of the switch matrix, and output second optical signals that are based at least partially on the first optical signals. The lens is configured to transform wave formats of the second optical signals based on the output ports over which the second optical signals are received. The transmitter includes an antenna array and circuitry coupled to the array. The circuitry is configured to receive the second optical signals from the lens, convert the second optical signals into beamformed wireless signals in accordance with the transformed formats, and transmit the beamformed wireless signals, which signals have spatial characteristics in accordance with the transformed formats, over the array.Type: GrantFiled: December 3, 2021Date of Patent: July 30, 2024Assignees: FUTUREWEI TECHNOLOGIES, INC., PHASE SENSITIVE INNOVATIONS, INC.Inventors: Stefano Galli, Munawar Kermalli, Xiao-Feng Qi, Shouyuan Shi, Dennis Prather, Janusz Murakowski, Garrett Schneider
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Publication number: 20240020044Abstract: A method for locating a hard disk applied in a server which governs many hard disks including some making use of one HD slot by an expander customizes the SCSI Enclosure Services (SES) custom page of an expander of a JBOD device, and obtains and stores 5 information of the JBOD device through the expander. The server further obtains information of a hard disk to be located, and obtains information of the JBOD device hosting the hard disk to be located according to the information of the hard disk to be located.Type: ApplicationFiled: November 10, 2022Publication date: January 18, 2024Inventors: JIE YUAN, SHI-QI CHEN
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Publication number: 20240011124Abstract: The present invention relates to a method and device for preparing an ultrathin metal lithium foil. With regard to the problems of lithium preparation processes in the prior art having a high lithium preparation reaction temperature, a low lithium recovery rate, low purity in collected lithium foils, a complicated process operation, etc., the present invention provides a method for preparing an ultrathin metal lithium foil, wherein firstly, a complex lithium salt is prepared, the complex lithium salt and a reducing agent are then subjected to a vacuum thermal reduction reaction so as to generate a metal vapor, the metal vapor is then subjected to vacuum distillation, and finally, vacuum evaporation is used to prepare the ultrathin metal lithium foil of the present invention.Type: ApplicationFiled: November 1, 2021Publication date: January 11, 2024Applicant: SHENZHEN YANYI NEW MATERIALS CO., LTD.Inventors: Kai YANG, Shi-Qi ZHANG, Wei-Jing FENG, Xiao-Fei ZHANG, Chao QIAN, Min YUE, Bo LIU
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Patent number: 11868758Abstract: A method to improve the updating of firmware in a firmware updating system, uses serially-sent data packets containing the update and data. The firmware updating system includes storage, including an expander/switch, a baseboard manager controller (BMC), and a storage interface. A universal asynchronous receiver/transmitter (UART) for serial communication in the expander/switch is initialized and firmware updating instruction is sent to the expander/switch by the BMC. The firmware data packets are sent to the expander/switch by the BMC. A serial instruction to reset is sent to the expander/switch by the BMC and the BMC ends a communication with the UART serial. A firmware updating system applying the method is also provided.Type: GrantFiled: November 12, 2021Date of Patent: January 9, 2024Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Jie Yuan, Shi-Qi Chen
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Patent number: 11829616Abstract: A method for identifying a connection slot used by a hard disk includes determining the name of a program or system kernel connected to a hard disk; determining slot information corresponding to the kernel name; generating a soft link relating the kernel name to the slot information. The soft link has a relationship with and coexists with the kernel name. A terminal device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.Type: GrantFiled: March 28, 2022Date of Patent: November 28, 2023Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Jie Yuan, Shi-Qi Chen
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Publication number: 20230312644Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.Type: ApplicationFiled: March 9, 2023Publication date: October 5, 2023Inventors: Shi-Qi Peng, Ming Zhao, Jian-Hui Wu, Yu-Ji Wang, Qi-Qi Feng
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Patent number: 11740790Abstract: A method for monitoring hard disks, implemented in an electronic device, includes sequentially detecting a number of hard disk codes of hard disks recorded by a host bus adapter, and determining whether each hard disk code has a drive letter assigned; if one hard disk code is determined to not have a drive letter assigned, writing a first mark corresponding to the hard disk code in a register of the host bus adapter. When detection of all hard disk codes is completed, transmitting the first marks written in the register to a CPLD interface and detecting whether each hard disk corresponding to the first mark is in place. If one hard disk corresponding to the first mark is found to be in place, controlling the hard disk to output an alarm based on the first mark.Type: GrantFiled: January 2, 2022Date of Patent: August 29, 2023Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Jie Yuan, Shi-Qi Chen
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Publication number: 20230185464Abstract: A method for identifying a connection slot used by a hard disk includes determining the name of a program or system kernel connected to a hard disk; determining slot information corresponding to the kernel name; generating a soft link relating the kernel name to the slot information. The soft link has a relationship with and coexists with the kernel name. A terminal device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.Type: ApplicationFiled: March 28, 2022Publication date: June 15, 2023Inventors: JIE YUAN, SHI-QI CHEN
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Publication number: 20230116294Abstract: A method to improve the updating of firmware in a firmware updating system, uses serially-sent data packets containing the update and data. The firmware updating system includes storage, including an expander/switch, a baseboard manager controller (BMC), and a storage interface. A universal asynchronous receiver/transmitter (UART) for serial communication in the expander/switch is initialized and firmware updating instruction is sent to the expander/switch by the BMC. The firmware data packets are sent to the expander/switch by the BMC. A serial instruction to reset is sent to the expander/switch by the BMC and the BMC ends a communication with the UART serial. A firmware updating system applying the method is also provided.Type: ApplicationFiled: November 12, 2021Publication date: April 13, 2023Inventors: JIE YUAN, SHI-QI CHEN
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Publication number: 20230101977Abstract: A method for monitoring hard disks, implemented in an electronic device, includes sequentially detecting a number of hard disk codes of hard disks recorded by a host bus adapter, and determining whether each hard disk code has a drive letter assigned; if one hard disk code is determined to not have a drive letter assigned, writing a first mark corresponding to the hard disk code in a register of the host bus adapter. When detection of all hard disk codes is completed, transmitting the first marks written in the register to a CPLD interface and detecting whether each hard disk corresponding to the first mark is in place. If one hard disk corresponding to the first mark is found to be in place, controlling the hard disk to output an alarm based on the first mark.Type: ApplicationFiled: January 2, 2022Publication date: March 30, 2023Inventors: JIE YUAN, SHI-QI CHEN
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Patent number: 11462503Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.Type: GrantFiled: October 6, 2020Date of Patent: October 4, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
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Patent number: 11348936Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.Type: GrantFiled: December 30, 2019Date of Patent: May 31, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
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Patent number: 11342352Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.Type: GrantFiled: December 30, 2019Date of Patent: May 24, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
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Patent number: 11270770Abstract: Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.Type: GrantFiled: June 1, 2020Date of Patent: March 8, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Cheng Gan, Wei Liu, Shi Qi Huang, Shunfu Chen
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Patent number: 11205619Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.Type: GrantFiled: July 8, 2020Date of Patent: December 21, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
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Publication number: 20210355163Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.Type: ApplicationFiled: April 8, 2021Publication date: November 18, 2021Inventors: Shi-Qi PENG, Ming ZHAO, Jian-Hui WU, Yu-Ji WANG, Qi-Qi FENG
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Publication number: 20210343742Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Liang CHEN, Lei XUE, Wei LIU, Shi Qi HUANG
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Patent number: 11094714Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.Type: GrantFiled: December 30, 2019Date of Patent: August 17, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
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Patent number: D1049755Type: GrantFiled: June 7, 2022Date of Patent: November 5, 2024Assignee: Lagom Kitchen Co.Inventors: Allison Leigh Cummings, Benjamin Andrew Bangser, David Shark Tong, Shi Qi