Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.

Abstract: A portable air pump assembly is constructed with a power bank with flashlight, USB output, laptop output, a 12V appliance connection port, a jump start clamp, and an air pump with three adaptors for inflating different devices including car tires, inflatable toys, camping furniture and sports equipment. A portable air pump assembly comprising: an enclosed pistol shaped housing defining a central chamber adapted to hold a plurality of pump components the pump components comprising a driving assembly mounted inside said enclosed housing. A pivotal trigger assembly is mounted to the housing which controls power to said motor and a display cap mounted on the rear of said pistol shaped housing, the display cap showing pressure values generated by the pump mechanism, and a portable power source adapted to be connected with the electric motor through the universal connection port and a control circuit.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.

Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.

Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.

Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.

Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.

Abstract: The present invention provides a liquid crystal display device, which includes a plurality of pixel units arranged in a matrix form. Each of the pixel units further includes a first sub-pixel electrode and a second sub-pixel electrode. The first sub-pixel electrode is set at a central position of the pixel unit. The second sub-pixel electrode is circumferentially set along a circumference of the first sub-pixel electrode. With the above arrangement, the present invention improves the ? view angle characteristics of the liquid crystal display device to provide enhanced performance of displaying of the liquid crystal display device and thus improving quality of displaying.

Abstract: The present invention provides a liquid crystal display device, which includes a plurality of pixel units arranged in a matrix form. Each of the pixel units further includes a first sub-pixel electrode and a second sub-pixel electrode. The first sub-pixel electrode is set at a central position of the pixel unit. The second sub-pixel electrode is circumferentially set along a circumference of the first sub-pixel electrode. With the above arrangement, the present invention improves the ? view angle characteristics of the liquid crystal display device to provide enhanced performance of displaying of the liquid crystal display device and thus improving quality of displaying.

Abstract: The present invention provides for an improved package for a laser diode. The package has portions of its inner surfaces covered with a non-reflecting material, such as simple black paint, non-reflective metals or specific anti-reflection coatings. Such non-reflecting materials surprisingly enhances the performance of packaged laser diodes used as pumping lasers for fiber amplifiers, for example.