Patents by Inventor Shianling Wu

Shianling Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140143623
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: Syntest Technologies, Inc.
    Inventors: Nur A. TOUBA, Laung-Terng WANG, Shianling WU
  • Patent number: 8522096
    Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 27, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba, Michael S. Hsiao, Zhigang Jiang, Shianling Wu
  • Patent number: 8458544
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hao-Jan Chao, Shianling Wu
  • Patent number: 8418100
    Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 9, 2013
    Assignee: STARDFX Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba, Shianling Wu, Ravi Apte
  • Patent number: 8335954
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 18, 2012
    Assignee: Syntest Technologies, Inc.
    Inventors: Nur A. Touba, Laung-Terng Wang, Shianling Wu
  • Publication number: 20120266036
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 18, 2012
    Applicant: Syntest Technologies, Inc.
    Inventors: Nur A. TOUBA, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
  • Patent number: 8230282
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 24, 2012
    Assignee: Syntest Technologies, Inc.
    Inventors: Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
  • Publication number: 20120173940
    Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: StarDFX Technologies, Inc.
    Inventors: Laung-Terng WANG, Nur A. Touba, Zhigang Jiang, Shianling Wu, Ravi Apte
  • Publication number: 20120166903
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 28, 2012
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng WANG, Hao-Jan CHAO, Shianling WU
  • Publication number: 20120110402
    Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.
    Type: Application
    Filed: August 31, 2011
    Publication date: May 3, 2012
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur Touba, Michael S. Hsiao, Shianling Wu, Zhigang Jiang
  • Patent number: 8161441
    Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: April 17, 2012
    Assignee: STARDFX Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Ravi Apte
  • Patent number: 8091002
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: January 3, 2012
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
  • Publication number: 20110258501
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicant: Sytest Technologies, Inc.
    Inventors: Nur A. TOUBA, Laung-Terng WANG, Zhigang JIANG, Shianling WU, Jiangping YAN
  • Patent number: 7996741
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: August 9, 2011
    Assignee: Syntest Technologies, Inc.
    Inventors: Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
  • Patent number: 7945833
    Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: May 17, 2011
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Nur A. Touba, Boryau (Jack) Sheu, Shianling Wu, Zhigang Jiang
  • Publication number: 20110047426
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Inventors: Nur A. TOUBA, Laung-Terng Wang, Zhigang Jiang, Shianling Wu, Jianping Yan
  • Publication number: 20110022908
    Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Applicant: StarDFX Technologies, Inc.
    Inventors: Laung-Terng WANG, Nur A. Touba, Zhigang Jiang, Shianling Wu, Ravi Apte
  • Publication number: 20110022907
    Abstract: A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 19, 2010
    Publication date: January 27, 2011
    Applicant: StarDFX Technologies, Inc.
    Inventors: Zhigang Jiang, Shianling Wu, Samy Makar, Laung-Terng Wang
  • Publication number: 20100287430
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: June 9, 2010
    Publication date: November 11, 2010
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng WANG, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
  • Patent number: 7783940
    Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 24, 2010
    Assignee: Syntest Technologies, Inc.
    Inventors: Lizhen Yu, Shianling Wu, Zhigang Jiang, Laung-Terng Wang