Abstract: A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

Abstract: A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.

Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. Two or more compressors are separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.

Abstract: A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus comprises two or more decompressors embedded between N compressed scan inputs and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows us to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. The method and apparatus further comprises two or more compressors separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.

Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.

Abstract: Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.

Abstract: A device (12), such as an A/D converter for generating successive codes, each in accordance with the level of an input analog voltage, may be tested to determine if all codes have been generated by applying a voltage V.sub.t having an amplitude that varies between 0 and V volts. The variation in the voltage V.sub.t is such that when the device (12) is operating properly, it will generate all of its codes during a predetermined interval. Each code generated by the device (12) is compared by a comparator (18) to the count of an n-bit counter (20) whose count is initialized at zero. Each time the count of the counter (20) matches the code produced by the device (12), the counter is incremented. If the counter overflows (i.e., its count has exceeded 2.sup.n -1) within a prescribed interval, then the device (12) is said to be operating properly.