Abstract: A vertical gallium oxide transistor and a preparation method thereof are provided. The method includes: annealing a gallium oxide material in an oxygen atmosphere at a range of temperature of 1000 to 1400° C. for 1 to 24 h so as to form a single crystal layer, a defective layer and an oxidized layer; removing the defective layer and the oxidized layer on a back of the gallium oxide material and the defective layer on a front of the gallium oxide material so as to obtain an initial sample; and preparing a heavily doped contact layer on the oxidized layer, preparing a source electrode layer on the contact layer, and preparing a trench perpendicular to a plane of the sample, and preparing a gate dielectric layer in the trench to fabricate a gate electrode and a drain electrode.

Abstract: A preparation method of a gallium oxide device based on high-temperature annealing technology and a gallium oxide device are provided. The preparation method includes: preparing a first barrier layer on a surface of a gallium oxide wafer to block an oxygen atmosphere; implementing a patterning process for regulating impurities of the gallium oxide wafer on the barrier layer, a process depth of the patterning process not exceeding a thickness of the barrier layer; annealing the gallium oxide wafer subjected to above treatment in the oxygen atmosphere; removing the barrier layer; and removing a surface layer of the gallium oxide wafer with the barrier layer lifted off. Problems that a local region of a gallium oxide material cannot be treated alone and net carrier concentration in a selective region of the gallium oxide material cannot be regulated with high-temperature annealing technology in the oxygen atmosphere in related art are solved.

Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: A neuron circuit (100), including a memristive element (M1), a trigger element (D1), a feedback element (T1) and an AND circuit (A1). The memristive element (M1) is used to receive an excitation signal. The trigger element (D1) is connected to the memristive element (M1) and is used to receive a clock control signal for the neuron circuit and an output signal of the memristive element (M1). The feedback element (T1) is connected to an output end of the trigger element (D1) and an input end of the memristive element (M1) and is used to control a voltage at the input end of the memristive element (M1). The AND circuit (A1) is used to perform an AND operation on an output signal of the trigger element (D1) and the clock control signal. An output signal of the AND circuit (A1) acts as an output signal of the neuron circuit (100).

Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer.

Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory.

Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.

Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration.

Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk.

Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.

Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: forming a copper wire in a groove through a Damascus copper interconnection process, wherein the copper wire includes a lower copper electrode for growing a storage medium, and the copper wire is arranged above a first capping layer; forming a second capping layer above the copper wire; forming a hole at a position corresponding to the lower copper electrode on the second capping layer, wherein the pore is used for exposing the lower copper electrode; performing composition and a chemical combination treatment on the lower copper electrode to generate a compound barrier layer, wherein the compound barrier layer is a compound formed by the chemical combination of elements Cu, Si and N, or a compound formed by the chemical combination of elements Cu, Ge and N; and depositing a solid electrolyte material and an upper electrode on the compound barrier layer.

Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal.

Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.

Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer.