Patents by Inventor Shieh-Hsing Kuo

Shieh-Hsing Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11943077
    Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 26, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
  • Patent number: 11888755
    Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 30, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
  • Patent number: 11750434
    Abstract: A multidrop network system includes N network devices including a master device and a plurality of slave devices. The N network devices synchronize their respective time zones in a synchronization phase, then jointly perform equalizer coefficient training in a training phase, and then obtain their respective transmission opportunities in turn in a data transmission phase. Each network device includes a channel equalizer trained in the training phase and used for processing data in the data transmission phase. In the training phase, the master device sends out a training notification to request the slave devices to enter the training phase; the master device performs the equalizer coefficient training after it transmits the training notification, and the slave devices perform the equalizer coefficient training after they receive the training notification. After the completion of the equalizer coefficient training, the master device sends out a beacon to start the data transmission phase.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 5, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Le Chang, Li-Chung Chen, Yuan-Jih Chu, Shieh-Hsing Kuo
  • Publication number: 20230037027
    Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.
    Type: Application
    Filed: May 31, 2022
    Publication date: February 2, 2023
    Inventors: YUNG-LE CHANG, WEN-CHIH FANG, DENG-SHIAN WANG, SHIEH-HSING KUO
  • Publication number: 20230021997
    Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 26, 2023
    Inventors: YUNG-LE CHANG, WEN-CHIH FANG, DENG-SHIAN WANG, SHIEH-HSING KUO
  • Publication number: 20230010016
    Abstract: A multidrop network system includes N network devices including a master device and a plurality of slave devices. The N network devices synchronize their respective time zones in a synchronization phase, then jointly perform equalizer coefficient training in a training phase, and then obtain their respective transmission opportunities in turn in a data transmission phase. Each network device includes a channel equalizer trained in the training phase and used for processing data in the data transmission phase. In the training phase, the master device sends out a training notification to request the slave devices to enter the training phase; the master device performs the equalizer coefficient training after it transmits the training notification, and the slave devices perform the equalizer coefficient training after they receive the training notification. After the completion of the equalizer coefficient training, the master device sends out a beacon to start the data transmission phase.
    Type: Application
    Filed: March 17, 2022
    Publication date: January 12, 2023
    Inventors: YUNG-LE CHANG, LI-CHUNG CHEN, YUAN-JIH CHU, SHIEH-HSING KUO
  • Patent number: 9680673
    Abstract: A communication system comprises a packet stream transforming unit, a mapping unit and a transmission unit. The packet stream transforming unit is configured to receive a 4-bit packet stream and transform the 4-bit packet stream into a 6-bit packet stream. The mapping unit is configured to map the 6-bit packet stream into multiple ternary bit streams, and the mapping unit maps at least one idle symbol into the ternary bit streams according to at least one particular bit of the at least one idle symbol of the 6-bit packet stream. The transmission unit is configured to transmit the ternary bit streams to a remote communication device through a cable.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 13, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Heng Cheong Lao, Ta-Chin Tseng, Shieh-Hsing Kuo, Sheng-Fu Chuang
  • Publication number: 20160269204
    Abstract: A communication system comprises a packet stream transforming unit, a mapping unit and a transmission unit. The packet stream transforming unit is configured to receive a 4-bit packet stream and transform the 4-bit packet stream into a 6-bit packet stream. The mapping unit is configured to map the 6-bit packet stream into multiple ternary bit streams, and the mapping unit maps at least one idle symbol into the ternary bit streams according to at least one particular bit of the at least one idle symbol of the 6-bit packet stream. The transmission unit is configured to transmit the ternary bit streams to a remote communication device through a cable.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 15, 2016
    Inventors: HENG CHEONG LAO, Ta-Chin TSENG, Shieh-Hsing KUO, Sheng-Fu CHUANG
  • Patent number: 9413422
    Abstract: In a communication system, a timing-dependence cancelling module is included for cancelling timing-dependence of a transmission signal, so as to render a timing-dependent signal be capable of being utilized on communication systems. Besides, updating an echo cancelling parameter by applying an error difference variable and a data difference variable, or by directly decreasing a step-size coefficient, may also fulfill the purpose of reducing or eliminating timing dependence in a transmission signal of a communication system.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 9, 2016
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Ta-Chin Tseng, Ting-Fa Yu
  • Patent number: 9413573
    Abstract: An analog and digital auto-gain control method includes the steps of: providing a gain-mapping table; determining an analog gain level according to a power of a far-end transmitted signal; obtaining a gain-mapping value from the gain-mapping table according to the analog gain level; obtaining a digital gain value according to the gain-mapping value; and adjusting a gain of a digital signal according to the digital gain value. A receiver that performs the auto-gain control method is also disclosed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: August 9, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Wei Huang, Chih-Yung Shih, Shieh-Hsing Kuo
  • Patent number: 9386517
    Abstract: The present invention discloses an energy efficient network communication device comprising: a media-access-controller for outputting a transmission-end low power idle (LPI) indication and receiving a reception-end LPI indication; a media-independent-interface for generating a transmission-end LPI signal according to the transmission-end LPI indication, and generating the reception-end LPI indication according to a reception-end LPI signal; and a physical-layer-circuit, coupled to several pairs of transmission lines, for converting the transmission-end LPI signal into a transmission signal to send it to a reception end for requesting an LPI mode and receiving a reception signal from the reception end to convert it into the reception-end LPI signal.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 5, 2016
    Assignee: Realtek Semiconductor Corporation
    Inventors: Ta-Chin Tseng, Shieh-Hsing Kuo, Liang-Wei Huang, Heng Cheong Lao
  • Patent number: 9319353
    Abstract: A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: April 19, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Li-Han Liang, Tao-Chun Wang, Kuo-Nan Yang, Shieh-Hsing Kuo
  • Patent number: 9252994
    Abstract: A network apparatus, for processing a network signal and outputting an output signal, includes an asynchronous signal processing module, a sampling rate converter and a synchronous signal processing module. The asynchronous signal processing module operates in an asynchronous domain, and is utilized for receiving and processing the network signal to generate a first processed signal. The sampling rate converter is coupled to the asynchronous signal processing module, and is utilized for performing sampling rate conversion on the first processed signal to generate the output signal. A first operating frequency of the asynchronous signal processing module is different from a second operating frequency of the synchronous signal processing module.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 2, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Wei Huang, Chih-Yung Shih, Shieh-Hsing Kuo
  • Patent number: 9128719
    Abstract: A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 8, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Ta-Chin Tseng, Chi-Shun Weng, Shieh-Hsing Kuo
  • Patent number: 9122479
    Abstract: A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: September 1, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shieh-Hsing Kuo, Ming-Je Li, Shian-Ru Lin, Ting-Fa Yu
  • Patent number: 8897318
    Abstract: A network device includes a first transceiver unit, a second transceiver unit and a control unit. The first transceiver unit is utilized for processing a data corresponding to a first physical (PHY) layer via a first interface. The second transceiver unit is utilized for processing a data corresponding to a second PHY layer via a second interface. The control unit is utilized for processing a data corresponding to a media access control (MAC) layer, wherein the control unit connects with at least one of the first transceiver unit and the second transceiver unit with reference to a connection scheme.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 25, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Li-Han Liang, Tzu-Han Hsu
  • Patent number: 8891601
    Abstract: A transceiver in a communication system and a start-up method thereof are provided. The transceiver comprises an auto-negotiation circuit, a timing recovery circuit, an interference cancellation circuit and an equalizer. The auto-negotiation circuit performs an auto-negotiation procedure to determine whether the transceiver operates as a master or slave transceiver. If the transceiver operates as a slave transceiver, it executes a first stage and a second stage during the start-up process. In the first stage, the transceiver performs channel estimation to generate a channel estimation value, presets the parameters of the equalizer according to the channel estimation value, and trains the timing recovery circuit and the equalizer; in the second stage, the transceiver trains the interference cancellation circuit.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: November 18, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Ta-Chin Tseng, Ting-Fa Yu, Lie Way Fang, Shieh-Hsing Kuo
  • Patent number: 8867650
    Abstract: An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: October 21, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Chi-Shun Weng, Chun-Hung Liu
  • Patent number: 8788858
    Abstract: A network device, for supporting a power saving mechanism through an auto-negotiation of HDMI, includes a transmitting circuit and a receiving circuit. The transmitting circuit is arranged for generating a link pulse signal to a second network device, wherein the network device and the second network device perform the auto-negotiation of a network connection by using the link pulse signal through HDMI in order to support the power saving mechanism. After the receiving circuit of the network device receives another link pulse signal transmitted from the second network device through HDMI, the network device is controlled to be operated under the power saving mechanism.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 22, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Ming-Feng Hsu, Yuan-Jih Chu
  • Patent number: 8755291
    Abstract: Network interface apparatus with power management is disclosed, which comprises a physical layer circuit, for receiving a packet on a network; a media access control circuit, for performing the media access processing on the packet to output a processed packet; an interface circuit, coupled to the media access control layer, for transmitting the processed packet to a bus; a detecting circuit, coupled to the physical layer circuit, for detecting a transmitting status of the packet on the network to output a detecting signal; a loading control circuit, coupled to the detecting circuit, for controlling a load positioned in the interface circuit according to the detecting signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 17, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Lie-Way Fang, Shieh-Hsing Kuo, Chia-Ying Chiu, Mei-chao Yeh