Abstract: A network device, for supporting a power saving mechanism through an auto-negotiation of HDMI, includes a transmitting circuit and a receiving circuit. The transmitting circuit is arranged for generating a link pulse signal to a second network device, wherein the network device and the second network device perform the auto-negotiation of a network connection by using the link pulse signal through HDMI in order to support the power saving mechanism. After the receiving circuit of the network device receives another link pulse signal transmitted from the second network device through HDMI, the network device is controlled to be operated under the power saving mechanism.

Abstract: A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism.

Abstract: A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result.

Abstract: A network device includes a first transceiver unit, a second transceiver unit and a control unit. The first transceiver unit is utilized for processing a data corresponding to a first physical (PHY) layer via a first interface. The second transceiver unit is utilized for processing a data corresponding to a second PHY layer via a second interface. The control unit is utilized for processing a data corresponding to a media access control (MAC) layer, wherein the control unit connects with at least one of the first transceiver unit and the second transceiver unit with reference to a connection scheme.

Abstract: In a communication system, a timing-dependence cancelling module is included for cancelling timing-dependence of a transmission signal, so as to render a timing-dependent signal be capable of being utilized on communication systems. Besides, updating an echo cancelling parameter by applying an error difference variable and a data difference variable, or by directly decreasing a step-size coefficient, may also fulfill the purpose of reducing or eliminating timing dependence in a transmission signal of a communication system.

Abstract: An EDC generating circuit includes a memory unit, an EDC generating module, a header generator and an EDC correcting circuit. The EDC generating module, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The header generator, which is coupled to the memory unit, is used for generating a header according to header information. The EDC correcting circuit, which is coupled to the memory unit, is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC.

Abstract: A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals.

Abstract: A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal.

Abstract: An encoding circuit is disclosed, which has a memory unit, an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit, and an encoder. The EDC generating circuit generates a first EDC according to at least one main data. The scrambler generates a scrambled main data according to the main data. The header generator generates a header according to header information. The EDC correcting circuit, corrects the first EDC according to the header to generate a second EDC. The encoder encodes an optical data according to the second EDC and the scrambled main data.

Abstract: An encoding circuit comprising: a memory unit; an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit and an decoder. The EDC generating circuit is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The scrambler is used for generating a scrambled main data according to the main data, and for storing the scrambled main data to the memory unit. The header generator is used for generating a header according to header information. The EDC correcting circuit is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC. The encoder is used for encoding optical data according to the second EDC and the scrambled main data.

Abstract: A network connection method with an auto-negotiation mechanism is applied to a first network apparatus, where the first network apparatus supports a plurality of connection modes, and the method includes: transmitting a plurality of indication signals to a second network apparatus to prepare to establish a link between the first network apparatus and the second network apparatus, where the plurality of indication signals correspond to the plurality of connection modes respectively; counting a number of times that the first network apparatus enters a transmit disable state to generate a counting value; and when the counting value reaches a threshold value, disabling a specific connection mode of the plurality of connection modes supported by the first network apparatus.

Abstract: The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold.

Abstract: An apparatus for channel interference cancellation includes a first interference-cancellation module and a first cancellation-signal generating circuit. The first interference-cancellation module comprises a first processing circuit including a grouping circuit and a first transforming circuit. The grouping circuit divides received data into a plurality of groups of first sub-data. The first transforming circuit sequentially transforms the groups of first sub-data from a first domain to a second domain to generate a plurality of groups of first transformed sub-data. The first cancellation-signal generating circuit comprises a delay unit, a first processing unit and a second processing unit. The delay unit sequentially delays the groups of first transformed sub-data to generate a plurality of groups of delayed sub-data. The first and the second processing unit output a first and a second processed signal according to the groups of first transformed sub-data and the groups of delayed sub-data respectively.

Abstract: A network apparatus with a plurality of transport ports and a shared coefficient update processor is proposed. Each of the plurality of transport ports includes a PHY module. The coefficient update processor is coupled to each PHY module and is shared by the plurality of transport ports. The coefficient update processor decides coefficients of each PHY module. The coefficient update processor is dedicated to one of the plurality of transport ports for use in a period of time.

Abstract: The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold.

Abstract: A communication signal receiver includes an adder, a slicer, and an infinite impulse response (IIR) filter. The adder performs an addition on a first signal and a filtered signal to generate an output signal. The slicer performs a hard decision on the output signal to generate a detecting result. The IIR filter is coupled to the slicer and the adder for processing the output signal to generate the filtered signal. The communication signal receiver further includes a decoder. The decoder receives and decodes the output signal to generate a decoded output signal, wherein the decoder is a Viterbi decoder.

Abstract: A network device, a network connection detector and a detection method thereof are disclosed. The network device includes a socket, a waveform generator and a reflected wave detector. The waveform generator sends a first test wave to at least a first contact of a plurality of contacts of a socket and then the reflected wave detector detects a first reflected wave that is corresponding to the first test wave and is reflected from the first contact. Thus a first control signal is generated according to detection result of the first reflected wave.

Abstract: The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold.

Abstract: An error correction device includes a decoding unit, an error buffer, an error classifying unit and an error correction unit. The decoding unit reads data from a main memory and performs error detection on the data to generate error values and error addresses. Then, the error buffer temporarily stores the error values and the error addresses. The error classifying unit classifies the error addresses stored in the error buffer into a plurality of subclasses, where error values and error addresses which correspond to the same row of the main memory are classified into the same subclass. Finally, the error correction unit performs an error correction on the data stored in the main memory according to the plurality of subclasses. The error correction device therefore can reduce the amount of the change-row operations of the main memory so that the memory efficiency is increased.

Abstract: Network interface apparatus with power management is disclosed, which comprises a physical layer circuit, for receiving a packet on a network; a media access control circuit, for performing the media access processing on the packet to output a processed packet; an interface circuit, coupled to the media access control layer, for transmitting the processed packet to a bus; a detecting circuit, coupled to the physical layer circuit, for detecting a transmitting status of the packet on the network to output a detecting signal; a loading control circuit, coupled to the detecting circuit, for control a load positioned in the interface circuit according to the detecting signal.