Patents by Inventor Shien-Yang Wu
Shien-Yang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8686536Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.Type: GrantFiled: April 30, 2010Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shien-Yang Wu, Wei-Chan Kung
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Patent number: 8629050Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: April 10, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry-Hak-Lay Chuang, Shien-Yang Wu, Shi-Bai Chen
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Publication number: 20130105895Abstract: A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact. The metal-semiconductor alloy layer is disposed over an epitaxial layer that is disposed over a fin structure of a substrate.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Minchang Liang, Shien-Yang Wu, Wei-Chang Kung
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Publication number: 20120196434Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
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Patent number: 8174091Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: July 15, 2009Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
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Patent number: 7952142Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.Type: GrantFiled: October 17, 2008Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shien-Yang Wu
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Publication number: 20110101493Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.Type: ApplicationFiled: April 30, 2010Publication date: May 5, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shien-Yang Wu, Wei-Chan Kung
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Patent number: 7898028Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.Type: GrantFiled: August 23, 2007Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sun-Jay Chang, Shien-Yang Wu
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Patent number: 7892895Abstract: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.Type: GrantFiled: August 19, 2005Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shien-Yang Wu, Shi-Bai Chen
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Publication number: 20100213569Abstract: An integrated circuit includes a fuse over a substrate. The fuse has a first end, a second end, and a central portion between the first end and the second end. A first dummy pattern is disposed adjacent to each side of the central portion of the fuse.Type: ApplicationFiled: December 15, 2009Publication date: August 26, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shien-Yang WU, Jye-Yen Cheng, Wei-Chan Kung
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Patent number: 7782073Abstract: A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.Type: GrantFiled: March 30, 2007Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tseng Chin Lo, Kuo-Tsai Li, Shien-Yang Wu
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Patent number: 7678655Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.Type: GrantFiled: July 28, 2006Date of Patent: March 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Der Su, Ju-Wang Hsu, Yi-Chun Huang, Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie, Yuan-Hung Chiu, Jyh-Huei Chen, Jhon Jhy Liaw
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Publication number: 20090273055Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: ApplicationFiled: July 15, 2009Publication date: November 5, 2009Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
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Publication number: 20090039445Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.Type: ApplicationFiled: October 17, 2008Publication date: February 12, 2009Inventor: Shien-Yang WU
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Patent number: 7456066Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.Type: GrantFiled: November 3, 2006Date of Patent: November 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shien-Yang Wu
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Publication number: 20080244475Abstract: A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data base which includes layout information of needed testlines.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Tseng Chin Lo, Kuo Tsai Li, Shien-Yang Wu
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Publication number: 20080238453Abstract: A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Tseng Chin Lo, Kuo-Tsai Li, Shien-Yang Wu
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Publication number: 20080122011Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.Type: ApplicationFiled: November 3, 2006Publication date: May 29, 2008Inventor: Shien-Yang Wu
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Patent number: 7332791Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.Type: GrantFiled: September 9, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shien-Yang Wu
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Publication number: 20080026518Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.Type: ApplicationFiled: July 28, 2006Publication date: January 31, 2008Inventors: Hung Der Su, Ju-Wang Hsu, Yi-Chun Huang, Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie, Yuan-Hung Chiu, Jyh-Huei Chen, Jhon Jhy Liaw