Abstract: An integrated circuit (IC) design system includes an IC design module for generating various portions of a mask layout according to a predefined specification of an integrated circuit, a mask module for assembling the various portions of the mask layout and forming a tape-out of the mask layout for mask manufacturing, and an e-LOP module operable to convert at least a subset of the various portions of the mask layout in a GDS format at a design stage prior to forming the tape-out.

Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.

Abstract: A fuse comprises a silicide element disposed above a substrate, a first terminal contact coupled to a first end of the silicide element, and a first metal line disposed above the silicide element and coupled to the first terminal contact. The fuse further comprises a plurality of second terminal contacts coupled to a second end of the silicide element, and a second metal line disposed above the silicide element and coupled to the plurality of second terminal contacts. The silicide element has a sufficient width that a programming potential applied across the first and second metal lines causes a discontinuity in the first terminal contact.

Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.

Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.

Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

Abstract: A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

Abstract: A programming method for fuse cells. A core circuit is applied with a first power voltage. The fuse cell includes an electrical fuse element connected to a common node, and a driver device connected between the electrical fuse element and a ground node. The ground node has a ground voltage. The fuse cell has a control gate for controlling current through the electrical fuse element. In program mode, a second power voltage is applied to the common node, a first control voltage is applied to the control gate of a selected fuse cell and a second control voltage is applied to the control gate of an unselected fuse cell. In read mode, the first power voltage is applied to the common node. The second power voltage exceeds the first power voltage. The second control voltage exceeds the ground voltage. The second control voltage is also lower than the first control voltage.

Abstract: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

Abstract: A fuse comprises a silicide element disposed above a substrate, a first terminal contact coupled to a first end of the silicide element, and a first metal line disposed above the silicide element and coupled to the first terminal contact. The fuse further comprises a plurality of second terminal contacts coupled to a second end of the silicide element, and a second metal line disposed above the silicide element and coupled to the plurality of second terminal contacts. The silicide element has a sufficient width that a programming potential applied across the first and second metal lines causes a discontinuity in the first terminal contact.

Abstract: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.

Abstract: A semiconductor device having a graded source/drain region for use in CMOS devices is provided. The semiconductor device is formed by utilizing a spacer and a sacrificial spacer as masks. The sacrificial spacer is formed over an etch stop layer, which acts as an etch stop and protects underlying structures from becoming damaged during the etching process. In particular, the present invention may be used, for example, to protect the edge or corner of a shallow trench isolation from becoming damaged during etching.

Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.

Abstract: An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

Abstract: An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.