Patents by Inventor Shige Furuta

Shige Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049469
    Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: June 29, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shige Furuta, Takahiro Yamaguchi, Hiroyuki Adachi, Shuji Nishi
  • Patent number: 11036106
    Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area is changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 15, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyoshi Kaise, Keiichi Ina, Yuhichiroh Murakami, Shige Furuta, Hidekazu Yamanaka
  • Publication number: 20210150999
    Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.
    Type: Application
    Filed: October 6, 2020
    Publication date: May 20, 2021
    Inventors: Yasushi SASAKI, Yuhichiroh MURAKAMI, Shige FURUTA, Takahiro YAMAGUCHI, Hiroyuki ADACHI, Shuji NISHI
  • Publication number: 20210141277
    Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 13, 2021
    Inventors: Yasuyoshi KAISE, Keiichi INA, Yuhichiroh MURAKAMI, Shige FURUTA, Hidekazu YAMANAKA
  • Publication number: 20210126017
    Abstract: The display device includes, on a substrate, a plurality of pixel electrodes, M (M is a natural number equal to or greater than three) counter electrodes disposed opposite the plurality of pixel electrodes, M counter electrode wiring lines connected with M counter electrodes, and N (N is a natural number and 2?N<M) common voltage wiring lines connected to the M counter electrode wiring lines. Counter electrode wiring lines connected to counter electrodes adjacent to each other are connected to common voltage wiring lines that are different from each other.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 29, 2021
    Inventors: Shige FURUTA, Hiroyuki ADACHI, Keiichi INA, Takahiro YAMAGUCHI, Yuhichiroh MURAKAMI
  • Publication number: 20210043152
    Abstract: A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 11, 2021
    Inventors: Takahiro YAMAGUCHI, Shuji NISHI, Shige FURUTA, Hiroyuki ADACHI, Nami NAGIRA
  • Patent number: 10847109
    Abstract: An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroyuki Adachi, Shige Furuta, Yuhichiroh Murakami, Hidekazu Yamanaka, Takahiro Yamaguchi, Kohei Hosoyachi
  • Patent number: 10706803
    Abstract: Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T2, T4, T9) whose on-off state is controlled at relatively high on-duty and a second group (T1, T3, T5, T6, T7, T8) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shige Furuta, Takahiro Yamaguchi, Junichi Yamada, Hidekazu Yamanaka, Yasushi Sasaki, Yuhichiroh Murakami
  • Publication number: 20200168173
    Abstract: An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 28, 2020
    Inventors: Hiroyuki ADACHI, Shige FURUTA, Yuhichiroh MURAKAMI, Hidekazu YAMANAKA, Takahiro YAMAGUCHI, Kohei HOSOYACHI
  • Publication number: 20200126466
    Abstract: On a panel substrate, there are a wide region where the wiring pitch between gate bus lines is relatively wide and a narrow region where the wiring pitch between the gate bus lines is relatively narrow. A shift register operates based on a gate start pulse signal and gate clock signals whose pulse widths are set to N (N is an integer not less than two) times a length of one horizontal scan period. A generation period of a pulse of a gate clock signal that brings one gate bus line constituting a gate bus line pair (two adjacent gate bus lines) into a selected state and a generation period of a pulse of a gate clock signal that brings the other gate bus line constituting the gate bus line pair into the selected state overlap for at least one horizontal scanning period.
    Type: Application
    Filed: June 8, 2018
    Publication date: April 23, 2020
    Inventors: KOHEI HOSOYACHI, SHIGE FURUTA, HIDEKAZU YAMANAKA, YUHICHIROH MURAKAMI
  • Publication number: 20190331974
    Abstract: Regarding a variant-form display (typically, a display device having a shape in which a non-display region is provided between display regions), it achieves a narrower picture-frame than conventional displays. In a display device having a non-rectangular display region, sub gate drivers are provided in a region where bypass wiring lines are conventionally disposed, for example, as follows. In a display device having a right-angled U-shaped display region having two projecting portions (a left projecting portion and a right projecting portion, a sub gate driver for driving some gate bus lines disposed in the left projecting portion is provided, in a region in a recessed portion, in a vicinity of the left projecting portion, and a sub gate driver for driving some gate bus lines disposed in the right projecting portion is provided, in a region in the recessed portion, in a vicinity of the right projecting portion.
    Type: Application
    Filed: August 1, 2017
    Publication date: October 31, 2019
    Inventors: Shige FURUTA, Yasushi SASAKI, Yuhichiroh MURAKAMI, Takahiro YAMAGUCHI, Junichi YAMADA, Hidekazu YAMANAKA
  • Patent number: 10410597
    Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr10 for supplying an off potential to a node n1 via a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr10. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr10. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Tr10 does not turn on and charge does not escape from the node 1. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: September 10, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuhichiroh Murakami, Shige Furuta, Hidekazu Yamanaka, Yasushi Sasaki
  • Publication number: 20190259347
    Abstract: A display device includes: an mth scanning signal line to which a plurality of sub pixels are connected; an nth scanning signal line to which a sub pixel is connected, the number of sub pixels which are connected to the nth scanning signal line being lower than the number of sub pixels which are connected to the mth scanning signal line; and a driver circuit which includes a plurality of output circuits and which drives the mth scanning signal line and the nth scanning signal line, an mth one of the plurality of output circuits including an mth output transistor connected to the mth scanning signal line, an nth one of the plurality of output circuits including an nth output transistor connected to the nth scanning signal line, a driving capability of the nth output transistor being lower than that of the mth output transistor.
    Type: Application
    Filed: January 3, 2019
    Publication date: August 22, 2019
    Inventors: Shige FURUTA, Nami NAGIRA, Hidekazu YAMANAKA, Yasuyoshi KAISE, Takahiro YAMAGUCHI, Kohei HOSOYACHI, Yuhichiroh MURAKAMI
  • Publication number: 20190259345
    Abstract: Luminance unevenness in a display area having an irregular shape is suppressed. An edge of the display area includes an irregularly-shaped edge which is curved. An end part of a signal switching circuit is located on an outer side of the irregularly-shaped edge. A driver is provided so as not to overlap with the end part of the signal switching circuit, as viewed in a first direction. An nth scanning signal line crosses the irregularly-shaped edge, passes through a space between the irregularly-shaped edge and the end part of the signal switching circuit, and is drawn to the driver, as viewed from above.
    Type: Application
    Filed: November 8, 2018
    Publication date: August 22, 2019
    Inventors: Kohei HOSOYACHI, Takahiro YAMAGUCHI, Shige FURUTA, Nami NAGIRA, Yuhichiroh MURAKAMI
  • Publication number: 20190259349
    Abstract: Luminance unevenness in a display area having an irregular shape is suppressed. A display panel is a display panel in which a cutout is provided, including: a display area in which sub pixels are provided; a non-display zone which is located between the cutout and the display area; a scanning signal line which is provided so as to pass through the display area and the non-display zone; an electric conductor which is at least partially located in the non-display zone; and an insulating film, the scanning signal line being provided so as to overlap with the electric conductor via the insulating film.
    Type: Application
    Filed: December 19, 2018
    Publication date: August 22, 2019
    Inventors: Yasuyoshi KAISE, Keiichi INA, Yoshimizu MORIYA, Ryohji YAYOTANI, Shige FURUTA, Hidekazu YAMANAKA
  • Patent number: 10347209
    Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr8 having a drain terminal connected to a node N2, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N2. The unit circuit 11 is further provided with a transistor Tr9 having a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node N2 to be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Tr8 before the initialization.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shige Furuta, Hidekazu Yamanaka
  • Publication number: 20190139617
    Abstract: A transistor includes gate electrodes and light blocking films. The light blocking films are provided in a layer lower than a layer in which the gate electrodes are provided, overlap the respective gate electrodes as viewed in a plan view, shield a channel portion from light, and are electrically isolated.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 9, 2019
    Inventors: YASUSHI SASAKI, YUHICHIROH MURAKAMI, SHIGE FURUTA, TAKAHIRO YAMAGUCHI
  • Patent number: 10241369
    Abstract: An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 26, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Etsuo Yamamoto, Hiroyuki Ohkawa, Shige Furuta
  • Patent number: 10228595
    Abstract: In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines, the plurality of source bus lines are wired to the plurality of layers such that taking source bus lines of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines to which positive video signals are applied matches the number of source bus lines to which negative video signals are applied in each of the layers in each of horizontal scanning periods.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 12, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Etsuo Yamamoto, Hiroyuki Ohkawa, Shige Furuta
  • Publication number: 20180149911
    Abstract: A drive circuit of a display device includes a TFT having a source electrode 15, a drain electrode 14, and a gate electrode 13. Provided is an electrically isolated light-shielding film 12 which has a main body portion for shielding a channel portion of the TFT, and an extension portion 20 formed integrally with the main body portion. An auxiliary capacitor C2 is formed by overlapping, in a planar view, the extension portion 20 with an electrode member 21 formed integrally with the source electrode 15. In place of the electrode member 21, an electrode member formed in a same layer as the channel portion and connected to the source electrode 15, an electrode member connected to one conduction electrode of another TFT, or an electrode member formed integrally with the gate electrode 13 may be used. With this, a small-area and low-cost drive circuit including a light-shielded thin film transistor is provided.
    Type: Application
    Filed: May 18, 2016
    Publication date: May 31, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TAKAHIRO YAMAGUCHI, SHIGE FURUTA, JUNICHI YAMADA, HIDEKAZU YAMANAKA, YUHICHIROH MURAKAMI, YASUSHI SASAKI