Abstract: In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

Abstract: A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

Abstract: A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14).

Abstract: In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.

Abstract: In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (?Vcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.

Abstract: A display driving circuit which carries out CC driving is configured such that a polarity of a data signal to be supplied to a source line is reversed every two horizontal scanning periods and a signal electric potential written from the source line to a pixel electrode changes in a different direction every two adjacent rows. In at least one example embodiment, this allows, in a display device which carries out CC driving, enhancement of a display quality by removing lateral stripes that are produced in a display video while n-line reversal driving is being carried out.

Abstract: A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

Abstract: A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

Abstract: Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.

Abstract: A retention circuit (22) corresponding to each stage of a shift register is configured such that, when SROUT(k?1) is active, an input terminal of an inverter (INV1) and an output terminal of an inverter (INV2) are electrically connected to each other and an output terminal of the inverter (INV1) and an input terminal of the inverter (INV2) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.

Abstract: This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.