Patents by Inventor Shigeaki Mashimo
Shigeaki Mashimo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9998032Abstract: In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin.Type: GrantFiled: September 12, 2017Date of Patent: June 12, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shigeaki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
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Publication number: 20180006578Abstract: In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin.Type: ApplicationFiled: September 12, 2017Publication date: January 4, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shigeaki MASHIMO, Fumio HORIUCHI, Kiyoaki KUDO, Akira SAKURAI, Yuhki INAGAKI
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Patent number: 9793826Abstract: In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. The circuit elements are mounted on upper surfaces of the island portions, and are connected to corresponding bonding portions by wirings. Two leads are adapted to be connected to positive and negative sides of a power source, and another lead is an output lead for providing alternating-current power. Lower surfaces of the island portions are attached to an upper surface of a circuit board. The circuit board, the circuit elements, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin.Type: GrantFiled: January 22, 2016Date of Patent: October 17, 2017Assignee: Semiconductor Components Industries, LLCInventors: Shigeaki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
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Patent number: 9722509Abstract: A circuit device comprises a circuit board and a plurality of leads each comprising an island portion, a bonding portion elevated from the island portion, and an oblique slope portion connecting the island portion and the bonding portion, and a plurality of circuit elements mounted on the island portions so as to be connected to corresponding bonding portions through wirings. Two leads are adapted to be connected to positive and negative electrodes of a direct-current power source, and yet another lead is an output lead adapted to output alternating-current power. One electrode provided on a transistor mounted on an island portion of the second input lead is connected to a bonding portion of the output lead through a wiring, and another electrode provided on a transistor mounted on an island portion of the output lead is connected to a bonding portion of the first input lead through a wiring.Type: GrantFiled: February 26, 2016Date of Patent: August 1, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shigeaki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
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Publication number: 20160248344Abstract: A circuit device comprises a circuit board and a plurality of leads each comprising an island portion, a bonding portion elevated from the island portion, and an oblique slope portion connecting the island portion and the bonding portion, and a plurality of circuit elements mounted on the island portions so as to be connected to corresponding bonding portions through wirings. Two leads are adapted to be connected to positive and negative electrodes of a direct-current power source, and yet another lead is an output lead adapted to output alternating-current power. One electrode provided on a transistor mounted on an island portion of the second input lead is connected to a bonding portion of the output lead through a wiring, and another electrode provided on a transistor mounted on an island portion of the output lead is connected to a bonding portion of the first input lead through a wiring.Type: ApplicationFiled: February 26, 2016Publication date: August 25, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shigeaki MASHIMO, Fumio HORIUCHI, Kiyoaki KUDO, Akira SAKURAI, Yuhki INAGAKI
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Publication number: 20160211247Abstract: In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. The circuit elements are mounted on upper surfaces of the island portions, and are connected to corresponding bonding portions by wirings. Two leads are adapted to be connected to positive and negative sides of a power source, and another lead is an output lead for providing alternating-current power. Lower surfaces of the island portions are attached to an upper surface of a circuit board. The circuit board, the circuit elements, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin.Type: ApplicationFiled: January 22, 2016Publication date: July 21, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shigeaki MASHIMO, Fumio HORIUCHI, Kiyoaki KUDO, Akira SAKURAI, Yuhki INAGAKI
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Patent number: 7276793Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: GrantFiled: February 8, 2005Date of Patent: October 2, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 7220921Abstract: In the present invention there is formed a sheet-like board member 50 having conductive coating films, such as first pads 55 and die pads 59, formed thereon or a sheet-like board member 50 which has been half-etched by using conductive coating films such as first pads 55 and die pads 59. A hybrid IC can be manufactured by means of utilization of post-processing processes of a semiconductor manufacturer. Further, a hybrid IC can be manufactured without adoption of a support board, and hence there can be manufactured a hybrid IC which is of lower profile and has superior heat dissipation characteristics.Type: GrantFiled: October 3, 2000Date of Patent: May 22, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 7173336Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: GrantFiled: January 17, 2003Date of Patent: February 6, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 7138296Abstract: A method of manufacturing a semiconductor device is described. A board that includes a flat back face, corresponding to a resin sealing area, and a front face that has projections is provided. The projections are formed of a metal that is integral with the board and include (a) a bonding pad provided in an area surrounded by an area that contacts an upper die, (b) a wiring that is integrated with the bonding pad and which extends to a semiconductor element mounting area, and (c) an electrode provided in one body with the wiring. A semiconductor element is mounted on the semiconductor element area and electrically connected to the bonding pad. The board is placed on a lower die and resin is filled into a space formed by the board and upper die. The board is divided into multiple devices such that the projections are separated by removing the board exposed at the back face of the resin.Type: GrantFiled: May 26, 2004Date of Patent: November 21, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 7125798Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: GrantFiled: February 24, 2003Date of Patent: October 24, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 7091606Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: GrantFiled: February 24, 2003Date of Patent: August 15, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 6975022Abstract: A device containing a flat member is provided, having a pattern for a bonding pad, a wiring, and an electrode, by half-etching through the flat member.Type: GrantFiled: March 16, 2001Date of Patent: December 13, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Publication number: 20050146052Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: ApplicationFiled: February 8, 2005Publication date: July 7, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Publication number: 20050056916Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: ApplicationFiled: August 13, 2004Publication date: March 17, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Publication number: 20040214374Abstract: By forming a flat member 10 forming a conductive film 11 having substantially same pattern with a second bonding pad 17, a wiring 18, and an electrode 19 for taking out , or forming a flat member 30 half-etched through the conductive film 11, it is possible to manufacture a semiconductor device 23 of BGA structure using a back process of a semiconductor maker.Type: ApplicationFiled: May 26, 2004Publication date: October 28, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Patent number: 6756610Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.Type: GrantFiled: March 12, 2003Date of Patent: June 29, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Kouji Takahashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa
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Publication number: 20030197199Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: ApplicationFiled: January 17, 2003Publication date: October 23, 2003Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
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Publication number: 20030170922Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.Type: ApplicationFiled: March 12, 2003Publication date: September 11, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Kouji Takahashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa
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Publication number: 20030160317Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: ApplicationFiled: February 24, 2003Publication date: August 28, 2003Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi