Patents by Inventor Shigekazu Okumura
Shigekazu Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11152210Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.Type: GrantFiled: December 15, 2020Date of Patent: October 19, 2021Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Patent number: 11043517Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.Type: GrantFiled: June 4, 2020Date of Patent: June 22, 2021Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Publication number: 20210143009Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.Type: ApplicationFiled: December 15, 2020Publication date: May 13, 2021Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Patent number: 10937647Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.Type: GrantFiled: February 11, 2019Date of Patent: March 2, 2021Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Patent number: 10886323Abstract: An infrared detector includes a pixel separation wall. The infrared detector includes a semiconductor crystal substrate; a first contact layer formed on the semiconductor crystal substrate, a pixel separation wall formed on the first contact layer and configured to separate pixels; a buffer layer formed on the first contact layer and on a side surface of the pixel separation wall in a region surrounded by the pixel separation wall, an infrared-absorbing layer formed on the buffer layer, a second contact layer formed on the infrared-absorbing layer, an upper electrode formed on the second contact layer, and a lower electrode formed on the first contact layer. The buffer layer and the first contact layer are formed of a compound semiconductor of a first conductivity type. The pixel separation wall and the second contact layer are formed of a compound semiconductor of a second conductivity type.Type: GrantFiled: June 12, 2019Date of Patent: January 5, 2021Assignee: FUJITSU LIMITEDInventor: Shigekazu Okumura
-
Publication number: 20200295059Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.Type: ApplicationFiled: June 4, 2020Publication date: September 17, 2020Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi TOMABECHI, RYO SUZUKI
-
Patent number: 10741714Abstract: An infrared detection device includes a semiconductor substrate; a first metamorphic buffer layer that is formed on the semiconductor substrate; a first contact layer that is formed on the first metamorphic buffer layer; a first infrared absorption layer that is formed on the first contact layer; a second contact layer that is formed on the first infrared absorption layer; a second metamorphic buffer layer that is formed on the second contact layer; a third contact layer that is formed on the second metamorphic buffer layer; a second infrared absorption layer that is formed on the third contact layer; a fourth contact layer that is formed on the second infrared absorption layer; a lower electrode that is connected with the first contact layer; an upper electrode that is connected with the fourth contact layer; and an intermediate electrode that is connected with the second contact layer and the third contact layer.Type: GrantFiled: June 13, 2019Date of Patent: August 11, 2020Assignee: FUJITSU LIMITEDInventor: Shigekazu Okumura
-
Patent number: 10720455Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.Type: GrantFiled: April 13, 2017Date of Patent: July 21, 2020Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Publication number: 20200194556Abstract: An apparatus includes a semiconductor substrate, a semiconductor layer, and a first conduction-type contact layer. The semiconductor layer that is provided above the semiconductor substrate, has a lattice constant different from a lattice constant of indium arsenide (InAs), and is formed from a semiconductor containing antimonide (Sb). The first conduction-type contact layer including a first conduction-type InAsSb layer provided over the semiconductor layer and a first conduction-type InAs layer provided over the first conduction-type InAsSb layer.Type: ApplicationFiled: November 22, 2019Publication date: June 18, 2020Applicant: FUJITSU LIMITEDInventor: Shigekazu Okumura
-
Patent number: 10580916Abstract: An infrared detector includes, a substrate, a lower contact layer formed on the substrate, a first light receiving layer that is formed on the lower contact layer and has a quantum well structure, an intermediate contact layer formed on the first light receiving layer, a second light receiving layer that is formed on the intermediate contact layer and has a quantum well structure, and an upper contact layer formed on the second light receiving layer. Each of the first light receiving layer and the second light receiving layer includes, a first semiconductor layer that is doped with a first conductivity-type impurity, and a second semiconductor layer that is formed on the first semiconductor layer, and is doped with a second conductivity-type impurity which compensates the first conductivity-type impurity.Type: GrantFiled: January 3, 2019Date of Patent: March 3, 2020Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Ryo Suzuki
-
Publication number: 20200035725Abstract: An apparatus includes a substrate that has a plane orientation inclined from a (100) plane such that an inclination angle to a [0-11] direction or a [01-1] direction is larger than an inclination angle to a [011] direction and a [0-1-1] direction, or inclined from a (010) plane such that an inclination angle to a [10-1] direction or a [?101] direction is larger than an inclination angle to a [101] direction and a [?10-1] direction, or inclined from a (001) plane such that an inclination angle to a [?110] direction or a [1-10] direction is larger than an inclination angle to a [110] direction and the [?1-10] direction; and a light-receiving layer disposed above the substrate and having a structure in which a plurality of semiconductor layers are stacked.Type: ApplicationFiled: July 1, 2019Publication date: January 30, 2020Applicant: FUJITSU LIMITEDInventors: Ryo Suzuki, Shigekazu Okumura, Koji Tsunoda
-
Publication number: 20200013822Abstract: An infrared detector includes a pixel separation wall. The infrared detector includes a semiconductor crystal substrate; a first contact layer formed on the semiconductor crystal substrate, a pixel separation wall formed on the first contact layer and configured to separate pixels; a buffer layer formed on the first contact layer and on a side surface of the pixel separation wall in a region surrounded by the pixel separation wall, an infrared-absorbing layer formed on the buffer layer, a second contact layer formed on the infrared-absorbing layer, an upper electrode formed on the second contact layer, and a lower electrode formed on the first contact layer. The buffer layer and the first contact layer are formed of a compound semiconductor of a first conductivity type. The pixel separation wall and the second contact layer are formed of a compound semiconductor of a second conductivity type.Type: ApplicationFiled: June 12, 2019Publication date: January 9, 2020Applicant: FUJITSU LIMITEDInventor: Shigekazu Okumura
-
Publication number: 20200013914Abstract: An infrared detection device includes a semiconductor substrate; a first metamorphic buffer layer that is formed on the semiconductor substrate; a first contact layer that is formed on the first metamorphic buffer layer; a first infrared absorption layer that is formed on the first contact layer; a second contact layer that is formed on the first infrared absorption layer; a second metamorphic buffer layer that is formed on the second contact layer; a third contact layer that is formed on the second metamorphic buffer layer; a second infrared absorption layer that is formed on the third contact layer; a fourth contact layer that is formed on the second infrared absorption layer; a lower electrode that is connected with the first contact layer; an upper electrode that is connected with the fourth contact layer; and an intermediate electrode that is connected with the second contact layer and the third contact layer.Type: ApplicationFiled: June 13, 2019Publication date: January 9, 2020Applicant: FUJITSU LIMITEDInventor: Shigekazu Okumura
-
Publication number: 20190319143Abstract: A semiconductor crystal substrate includes: a crystal substrate whose principal surface is inclined relative to a (001) plane; and a superlattice structure layer including a first superlattice formation layer and a second superlattice formation layer, wherein the first superlattice formation layer is formed of Ga1-x1Inx1Asy1Sb1-y1 (0?x1?0.1, 0?y1?0.1), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.20, and the second superlattice formation layer is formed of Ga1-x2Inx2Asy2Sb1-y2 (0.9?x2?1, 0.9?y2?1), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.40.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi
-
Publication number: 20190221693Abstract: An infrared detector includes, a substrate, a lower contact layer formed on the substrate, a first light receiving layer that is formed on the lower contact layer and has a quantum well structure, an intermediate contact layer formed on the first light receiving layer, a second light receiving layer that is formed on the intermediate contact layer and has a quantum well structure, and an upper contact layer formed on the second light receiving layer. Each of the first light receiving layer and the second light receiving layer includes, a first semiconductor layer that is doped with a first conductivity-type impurity, and a second semiconductor layer that is formed on the first semiconductor layer, and is doped with a second conductivity-type impurity which compensates the first conductivity-type impurity.Type: ApplicationFiled: January 3, 2019Publication date: July 18, 2019Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, RYO SUZUKI
-
Publication number: 20190214252Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.Type: ApplicationFiled: February 11, 2019Publication date: July 11, 2019Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
-
Patent number: 10340399Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).Type: GrantFiled: July 28, 2016Date of Patent: July 2, 2019Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
-
Publication number: 20190006532Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).Type: ApplicationFiled: July 28, 2016Publication date: January 3, 2019Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
-
Publication number: 20170366075Abstract: A synchronous reluctance motor includes: an annular stator; and a rotor disposed radially inside the stator. The stator includes an annular stator core having in its inner peripheral portion a plurality of slots located at intervals in a circumferential direction of the stator, and slot coils accommodated in the slots. The slot coils are formed by a wire having a quadrilateral section and are wound in the slots by distributed winding.Type: ApplicationFiled: June 13, 2017Publication date: December 21, 2017Applicant: JTEKT CORPORATIONInventors: Mingyu TONG, Ken MATSUBARA, Yuji KARIATSUMARI, Hirohide INAYAMA, Shigekazu OKUMURA, Ryosuke YAMAGUCHI
-
Publication number: 20170358613Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.Type: ApplicationFiled: April 13, 2017Publication date: December 14, 2017Applicant: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi TOMABECHI, RYO SUZUKI