Patents by Inventor Shigekazu Okumura

Shigekazu Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035725
    Abstract: An apparatus includes a substrate that has a plane orientation inclined from a (100) plane such that an inclination angle to a [0-11] direction or a [01-1] direction is larger than an inclination angle to a [011] direction and a [0-1-1] direction, or inclined from a (010) plane such that an inclination angle to a [10-1] direction or a [?101] direction is larger than an inclination angle to a [101] direction and a [?10-1] direction, or inclined from a (001) plane such that an inclination angle to a [?110] direction or a [1-10] direction is larger than an inclination angle to a [110] direction and the [?1-10] direction; and a light-receiving layer disposed above the substrate and having a structure in which a plurality of semiconductor layers are stacked.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 30, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Ryo Suzuki, Shigekazu Okumura, Koji Tsunoda
  • Publication number: 20200013914
    Abstract: An infrared detection device includes a semiconductor substrate; a first metamorphic buffer layer that is formed on the semiconductor substrate; a first contact layer that is formed on the first metamorphic buffer layer; a first infrared absorption layer that is formed on the first contact layer; a second contact layer that is formed on the first infrared absorption layer; a second metamorphic buffer layer that is formed on the second contact layer; a third contact layer that is formed on the second metamorphic buffer layer; a second infrared absorption layer that is formed on the third contact layer; a fourth contact layer that is formed on the second infrared absorption layer; a lower electrode that is connected with the first contact layer; an upper electrode that is connected with the fourth contact layer; and an intermediate electrode that is connected with the second contact layer and the third contact layer.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 9, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20200013822
    Abstract: An infrared detector includes a pixel separation wall. The infrared detector includes a semiconductor crystal substrate; a first contact layer formed on the semiconductor crystal substrate, a pixel separation wall formed on the first contact layer and configured to separate pixels; a buffer layer formed on the first contact layer and on a side surface of the pixel separation wall in a region surrounded by the pixel separation wall, an infrared-absorbing layer formed on the buffer layer, a second contact layer formed on the infrared-absorbing layer, an upper electrode formed on the second contact layer, and a lower electrode formed on the first contact layer. The buffer layer and the first contact layer are formed of a compound semiconductor of a first conductivity type. The pixel separation wall and the second contact layer are formed of a compound semiconductor of a second conductivity type.
    Type: Application
    Filed: June 12, 2019
    Publication date: January 9, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20190319143
    Abstract: A semiconductor crystal substrate includes: a crystal substrate whose principal surface is inclined relative to a (001) plane; and a superlattice structure layer including a first superlattice formation layer and a second superlattice formation layer, wherein the first superlattice formation layer is formed of Ga1-x1Inx1Asy1Sb1-y1 (0?x1?0.1, 0?y1?0.1), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.20, and the second superlattice formation layer is formed of Ga1-x2Inx2Asy2Sb1-y2 (0.9?x2?1, 0.9?y2?1), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.40.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi
  • Publication number: 20190221693
    Abstract: An infrared detector includes, a substrate, a lower contact layer formed on the substrate, a first light receiving layer that is formed on the lower contact layer and has a quantum well structure, an intermediate contact layer formed on the first light receiving layer, a second light receiving layer that is formed on the intermediate contact layer and has a quantum well structure, and an upper contact layer formed on the second light receiving layer. Each of the first light receiving layer and the second light receiving layer includes, a first semiconductor layer that is doped with a first conductivity-type impurity, and a second semiconductor layer that is formed on the first semiconductor layer, and is doped with a second conductivity-type impurity which compensates the first conductivity-type impurity.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 18, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, RYO SUZUKI
  • Publication number: 20190214252
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.
    Type: Application
    Filed: February 11, 2019
    Publication date: July 11, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 10340399
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 2, 2019
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Publication number: 20190006532
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Application
    Filed: July 28, 2016
    Publication date: January 3, 2019
    Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Publication number: 20170366075
    Abstract: A synchronous reluctance motor includes: an annular stator; and a rotor disposed radially inside the stator. The stator includes an annular stator core having in its inner peripheral portion a plurality of slots located at intervals in a circumferential direction of the stator, and slot coils accommodated in the slots. The slot coils are formed by a wire having a quadrilateral section and are wound in the slots by distributed winding.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 21, 2017
    Applicant: JTEKT CORPORATION
    Inventors: Mingyu TONG, Ken MATSUBARA, Yuji KARIATSUMARI, Hirohide INAYAMA, Shigekazu OKUMURA, Ryosuke YAMAGUCHI
  • Publication number: 20170358613
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Application
    Filed: April 13, 2017
    Publication date: December 14, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi TOMABECHI, RYO SUZUKI
  • Patent number: 9577136
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20160293788
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 9401447
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20160043262
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 11, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 8987117
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
  • Patent number: 8767364
    Abstract: When a short-circuited FET is identified as one of low-side FETs, maximum phase voltages of three phases are detected when a steering operation is performed by a driver, and the detected maximum phase voltages of the three phases are compared with one another to identify a short-circuit phase. On the other hand, when a short-circuited FET is identified as one of high-side FETs, minimum phase voltages of the three phases are detected when a steering operation is performed by the driver, and the detected minimum phase voltages of the three phases are compared with one another to identify a short-circuit phase.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 1, 2014
    Assignee: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Patent number: 8736208
    Abstract: When one of six FETs has short-circuit faulted, a controllable region identification unit stops driving of an electric motor, and then performs processes for determining whether a short-circuit fault has occurred, and when a short-circuit fault has occurred, for identifying the position of the FET that has short-circuit faulted based on phase voltages (induced voltages) VU, VV, and VW of phases. When the position of the FET that has short-circuit faulted is identified, the controllable region identification unit performs a controllable region identification process. In detail, the controllable region identification unit identifies a “possible region,” an “indeterminate region,” and a “impossible region” based on phase voltages VU, VV, and VW of the phases.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Jtekt Corporation
    Inventors: Shigekazu Okumura, Fumihiko Satou, Hiroshi Sumasu
  • Patent number: 8716967
    Abstract: A motor control device for controlling a three-phase brushless motor that has a rotor and field coils includes: a load range determining unit that determines a rotor rotation angle range, in which the three-phase brushless motor becomes a load, as a load range when a short-circuit fault occurs in one of a plurality of switching elements. The load range determining unit determines a rotor rotation angle range, in which load current is presumed to flow through a closed circuit formed of the short-circuit switching element and any one of regenerative diodes connected in parallel with the respective normal switching elements when the rotor is rotated in a state where all the switching elements other than the short-circuit switching element are turned off, as the load range.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 6, 2014
    Assignee: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Publication number: 20130330867
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu OKUMURA, Mitsuru EKAWA, Shuichi TOMABECHI, Ayahito UETAKE
  • Patent number: 8565279
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Fujitsu Limited
    Inventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake