Patents by Inventor Shigekazu Okumura

Shigekazu Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9577136
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20160293788
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 9401447
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Publication number: 20160043262
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 11, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 8987117
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
  • Patent number: 8767364
    Abstract: When a short-circuited FET is identified as one of low-side FETs, maximum phase voltages of three phases are detected when a steering operation is performed by a driver, and the detected maximum phase voltages of the three phases are compared with one another to identify a short-circuit phase. On the other hand, when a short-circuited FET is identified as one of high-side FETs, minimum phase voltages of the three phases are detected when a steering operation is performed by the driver, and the detected minimum phase voltages of the three phases are compared with one another to identify a short-circuit phase.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 1, 2014
    Assignee: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Patent number: 8736208
    Abstract: When one of six FETs has short-circuit faulted, a controllable region identification unit stops driving of an electric motor, and then performs processes for determining whether a short-circuit fault has occurred, and when a short-circuit fault has occurred, for identifying the position of the FET that has short-circuit faulted based on phase voltages (induced voltages) VU, VV, and VW of phases. When the position of the FET that has short-circuit faulted is identified, the controllable region identification unit performs a controllable region identification process. In detail, the controllable region identification unit identifies a “possible region,” an “indeterminate region,” and a “impossible region” based on phase voltages VU, VV, and VW of the phases.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Jtekt Corporation
    Inventors: Shigekazu Okumura, Fumihiko Satou, Hiroshi Sumasu
  • Patent number: 8716967
    Abstract: A motor control device for controlling a three-phase brushless motor that has a rotor and field coils includes: a load range determining unit that determines a rotor rotation angle range, in which the three-phase brushless motor becomes a load, as a load range when a short-circuit fault occurs in one of a plurality of switching elements. The load range determining unit determines a rotor rotation angle range, in which load current is presumed to flow through a closed circuit formed of the short-circuit switching element and any one of regenerative diodes connected in parallel with the respective normal switching elements when the rotor is rotated in a state where all the switching elements other than the short-circuit switching element are turned off, as the load range.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 6, 2014
    Assignee: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Publication number: 20130330867
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu OKUMURA, Mitsuru EKAWA, Shuichi TOMABECHI, Ayahito UETAKE
  • Patent number: 8565279
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Fujitsu Limited
    Inventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
  • Publication number: 20130010824
    Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 10, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shigekazu OKUMURA, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
  • Publication number: 20130003232
    Abstract: When a short-circuited FET is identified as one of low-side FETs, maximum phase voltages of three phases are detected when a steering operation is performed by a driver, and the detected maximum phase voltages of the three phases are compared with one another to identify a short-circuit phase. On the other hand, when a short-circuited FET is identified as one of high-side FETs, minimum phase voltages of the three phases are detected when a steering operation is performed by the driver, and the detected minimum phase voltages of the three phases are compared with one another to identify a short-circuit phase.
    Type: Application
    Filed: June 14, 2012
    Publication date: January 3, 2013
    Applicant: JTEKT CORPORATION
    Inventor: Shigekazu OKUMURA
  • Publication number: 20120326644
    Abstract: When one of six FETs has short-circuit faulted, a controllable region identification unit stops driving of an electric motor, and then performs processes for determining whether a short-circuit fault has occurred, and when a short-circuit fault has occurred, for identifying the position of the FET that has short-circuit faulted based on phase voltages (induced voltages) VU, VV, and VW of phases. When the position of the FET that has short-circuit faulted is identified, the controllable region identification unit performs a controllable region identification process. In detail, the controllable region identification unit identifies a “possible region,” an “indeterminate region,” and a “impossible region” based on phase voltages VU, VV, and VW of the phases.
    Type: Application
    Filed: March 25, 2011
    Publication date: December 27, 2012
    Applicant: JTEKT CORPORATION
    Inventors: Shigekazu Okumura, Fumihiko Satou, Hiroshi Sumasu
  • Publication number: 20110234130
    Abstract: A motor control device for controlling a three-phase brushless motor that has a rotor and field coils includes: a load range determining unit that determines a rotor rotation angle range, in which the three-phase brushless motor becomes a load, as a load range when a short-circuit fault occurs in one of a plurality of switching elements. The load range determining unit determines a rotor rotation angle range, in which load current is presumed to flow through a closed circuit formed of the short-circuit switching element and any one of regenerative diodes connected in parallel with the respective normal switching elements when the rotor is rotated in a state where all the switching elements other than the short-circuit switching element are turned off, as the load range.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Applicant: JTEKT CORPORATION
    Inventor: Shigekazu OKUMURA
  • Patent number: 7944163
    Abstract: A sensorless controlling apparatus for controlling a brushless motor includes a speed calculator for calculating speed of a rotor ?, an angle calculator for calculating rotor angle ? at a predetermined time interval, and an angle controller for calculating correction angle ?? based on the current value of a d-axis current (d-axis current value id), thereby controlling the rotor angle ?. The angle calculator uses the correction angle ?? calculated by the angle controller, the speed ? calculated by the speed calculator, a predetermined time, and the rotor angle ? calculated by the angle calculator at a predetermined time to calculate the rotor angle at the predetermined time interval. Thus, the rotor angle ? calculated by the angle calculator is converged on the true angle of the rotor.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: May 17, 2011
    Assignee: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Patent number: 7924896
    Abstract: An optical semiconductor device includes an active layer, a first semiconductor layer formed above the active layer and made from a semiconductor material containing Al, a second semiconductor layer formed above the first semiconductor layer and made from a semiconductor material which does not contain any one of Al and P and whose band gap is greater than that of the active layer, and a third semiconductor layer formed above the second semiconductor layer and made from a semiconductor material which does not contain Al but contains P. The second semiconductor layer is formed such that the first semiconductor layer and the third semiconductor layer do not contact with each other.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: April 12, 2011
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Manabu Matsuda, Mitsuru Ekawa, Kan Takada, Shigekazu Okumura
  • Publication number: 20090052487
    Abstract: An optical semiconductor device includes an active layer, a first semiconductor layer formed above the active layer and made from a semiconductor material containing Al, a second semiconductor layer formed above the first semiconductor layer and made from a semiconductor material which does not contain any one of Al and P and whose band gap is greater than that of the active layer, and a third semiconductor layer formed above the second semiconductor layer and made from a semiconductor material which does not contain Al but contains P. The second semiconductor layer is formed such that the first semiconductor layer and the third semiconductor layer do not contact with each other.
    Type: Application
    Filed: September 19, 2008
    Publication date: February 26, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Manabu Matsuda, Mitsuru Ekawa, Kan Takada, Shigekazu Okumura
  • Publication number: 20090033262
    Abstract: A sensorless controlling apparatus for controlling a brushless motor includes a speed calculator for calculating speed of a rotor ?, an angle calculator for calculating rotor angle ? at a predetermined time interval, and an angle controller for calculating correction angle ?? based on the current value of a d-axis current (d-axis current value id), thereby controlling the rotor angle ?. The angle calculator uses the correction angle ?? calculated by the angle controller, the speed ? calculated by the speed calculator, a predetermined time, and the rotor angle ? calculated by the angle calculator at a predetermined time to calculate the rotor angle at the predetermined time interval. Thus, the rotor angle ? calculated by the angle calculator is converged on the true angle of the rotor.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: JTEKT Corporation
    Inventor: Shigekazu Okumura
  • Publication number: 20070153448
    Abstract: A print board that is to be connected to a motor includes a wiring layer in which a driving current flows. A bolting through hole is provided close to the wiring layers. Meanwhile, a power terminal of the motor is in the form of nuts. A bolt is inserted into the through hole and is threaded into the power terminal.
    Type: Application
    Filed: December 15, 2006
    Publication date: July 5, 2007
    Applicants: JTEKT CORPORATION, KOYO ELECTRONICS INDUSTRIES CO., LTD.
    Inventors: Shigekazu Okumura, Daigo Itou