Abstract: A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

Abstract: A semiconductor device is provided which includes a memory part that includes memory cells having different threshold values; a read circuit that reads data from a memory cell to be programmed with write data that is input; and a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing. The pattern that causes erasing during the programming is processed as an inhibited operation. If the inhibited operation is identified, the process is forcedly terminated without initiating the programming by the write command. This makes it possible to avoid erasing resulting from the programming.

Abstract: A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted into information according to each level of the multi-level memory cell, a write circuit writing information into the multi-level memory cell on a group basis corresponding to the number of memory cells simultaneously programmable, according to the write information, and a control circuit controlling programming the memory cell array. The information is simultaneously programmed on the group basis into which multiple-word input information is divided, and makes it possible to shorten a program period substantially on a word basis.

Abstract: A semiconductor memory has regular sectors, a spare sector replaced from the regular sectors, and regular sector selection signal generating circuit and a spare sector selection signal generating circuit, which in response to an address change signal generate a regular sector selection signal and a spare sector selection signal. It also has a redundancy memory that stores replacement information read out in response to the address change signal, and a reference redundancy memory read out in response to the address change signal and generating an output signal that changes when this memory information readout is completed. Then, in response to the change in output signal of the reference redundancy memory, either the regular sector selection signal or the spare sector selection signal is set to the deselected state, based on the replacement information.

Abstract: A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

Abstract: A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node.

Abstract: The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.

Abstract: A semiconductor memory has regular sectors, a spare sector replaced from the regular sectors, and regular sector selection signal generating circuit and a spare sector selection signal generating circuit, which in response to an address change signal generate a regular sector selection signal and a spare sector selection signal. It also has a redundancy memory that stores replacement information read out in response to the address change signal, and a reference redundancy memory read out in response to the address change signal and generating an output signal that changes when this memory information readout is completed. Then, in response to the change in output signal of the reference redundancy memory, either the regular sector selection signal or the spare sector selection signal is set to the deselected state, based on the replacement information.

Abstract: A semiconductor device is provided which includes a memory part that includes memory cells having different threshold values; a read circuit that reads data from a memory cell to be programmed with write data that is input; and a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing. The pattern that causes erasing during the programming is processed as an inhibited operation. If the inhibited operation is identified, the process is forcedly terminated without initiating the programming by the write command. This makes it possible to avoid erasing resulting from the programming.

Abstract: A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a threshold voltage of the memory cell, and verify operation which is performed before and after the program operation in order to verify the threshold voltage of the memory cell. A drain switching circuit connects during the verify operation a gate of the transmission transistor to a first voltage line through which a first voltage is supplied, and it connects during the program operation the same to a second voltage line through which a second voltage is supplied. Since the second voltage can be supplied to the transmission transistor only by the switching operation (selecting operation) of the drain switching circuit, the program operation can be started shortly after the verify operation. This can shorten the data write time to the memory cell.

Abstract: A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data discriminating control unit generates an average reference level based on a reference level supplied from the first reference cell and a reference level supplied from the second reference cell, and the data discriminating control unit determining whether data is zero or one by comparison of a read-out level of each of the memory cells with the average reference level. A reference cell setting unit performs program verification for each memory cell with respect to a threshold level of the first reference cell to obtain a distribution of threshold levels of the memory cells, and the reference cell setting unit setting a threshold level of the second reference cell based on the distribution of the threshold levels of the memory cells.

Abstract: A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

Abstract: System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data discriminating control unit generates an average reference level based on a reference level supplied from the first reference cell and a reference level supplied from the second reference cell, and the data discriminating control unit determining whether data is zero or one by comparison of a read-out level of each of the memory cells with the average reference level. A reference cell setting unit performs program verification for each memory cell with respect to a threshold level of the first reference cell to obtain a distribution of threshold levels of the memory cells, and the reference cell setting unit setting a threshold level of the second reference cell based on the distribution of the threshold levels of the memory cells.

Abstract: System to set threshold voltages in a memory device. The system includes apparatus to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltage source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.

Abstract: System for setting reference cell threshold voltage of a memory device. The memory device includes a plurality of core cells and first and second reference cells all coupled to a common word line. The method comprises steps of programming the first reference cell to a first voltage threshold level that is centered within a data bit “1” distribution of the core cells, and programming the second reference cell to a second voltage threshold level that is centered within a data bit “0” distribution of the core cells.

Abstract: System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.