Abstract: System to program core cells in a memory device without over-programming. The system includes a method for programming a voltage threshold (Vt) level of a core cell in a memory device. The method comprises steps of determining a desired Vt for the core cell, programming a portion of the Vt of the core cell using a selected programming strength, verifying that the portion of the Vt is successfully programmed, adjusting the selected programming strength, and repeating the step of programming, verifying, and adjusting until the Vt of the core cell is substantially equal to the desired Vt.

Abstract: System to set threshold voltages in a memory device. The system includes apparatus to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltge source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.

Abstract: A system for reducing the recovery time for the second read in the double-bit cell of a semiconductor memory device. For reading the second bit of the double-bit cell, in addition to swapping the source and drain terminals of a core cell, the source and drain terminals of corresponding double-bit reference cells are also swapped. The system includes a circuit that effects the swapping by providing a path to enable reading the cells in the reverse direction for the second bit read. The swapping enables the bits of the core cell to be accurately determined over the life of the device while at the same time reducing the recovery time needed for execution of the read of the second bit of the double-bit cell.

Abstract: System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

Abstract: The present invention controls the ever-changing thermal crowns to give good strip shapes during rolling without causing any flaws in the rolled surfaces and with quick responses to ever-changing thermal crowns.

Abstract: System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

Abstract: The present invention discloses a voltage regulation method and system that provides a predetermined erase voltage to at least one wordline during a negative gate stress mode. A low-supply voltage negative charge pump is activated to generate a relatively high negative voltage. The relatively high negative voltage is regulated to the predetermined erase voltage by a regulator circuit. Regulation of the relatively high negative voltage is based on a variable reference voltage that is generated by a reference voltage circuit and directed to the regulator circuit. The predetermined reference voltage is capable of being varied within a first predetermined voltage range, thereby varying the predetermined erase voltage. The predetermined erase voltage is transferred to the wordlines by at least one decoder circuit during an erase operation.

Abstract: The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.

Abstract: The present invention controls the ever-changing thermal crowns to give good strip shapes during rolling without causing any flaws in the rolled surfaces and with quick responses to ever-changing thermal crowns.

Abstract: When an array VT test mode is entered, a predetermined wordline voltage is generated by a wordline voltage supply and supplied to at least one decoder circuit and a voltage control logic circuit. The voltage control logic circuit generates a predetermined control voltage that is directed to the decoder circuits. The predetermined control voltage activates the decoder circuits. A particular decoder circuit is electrically selected to decode at least one respective wordline and transfer the predetermined wordline voltage to the respective wordline. The activated decoder circuits that are not electrically selected are not forward-biased.

Abstract: A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.

Abstract: The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.

Abstract: A non-volatile semiconductor memory device includes a first memory cell which is electrically erasable and programmable and stores data, a second memory cell which is electrically erasable and programmable and has a threshold voltage which is set by performing erase and write operations on the second memory separately from erase and write operations on the first memory, and a sense amplifier comparing currents respectively flowing in the first and second memory cells to sense a state of the first memory cell. A verify voltage supply circuit supplies, in an erase verify operation, control gates of the first and second memory cells with erase verify voltages dependent on an actual value of the threshold voltage of the second memory cell, and supplies, in a write verify operation, the control gates of the first and second memory cells with write verify voltages dependent on an actual value of the threshold voltage of the second memory cell.

Abstract: At the time of erasing, the erase verification is not effected but the erase voltage is repetitively applied to the source of a memory cell until it is so judged that the erase current I.sub.A flowing into the source of the memory is smaller than the reference current I.sub.B and when it is judged that the erase current I.sub.A flowing into the source of the memory cell is smaller than the reference current I.sub.B, application of the erase pulse to the source of the memory cell and the erase verification are repetitively effected. As a result, in the flash memory device, it is possible to decrease the number of times of erase verification and reduce the time required for the erasing.