Patents by Inventor Shigeki Nakamura

Shigeki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150188436
    Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 2, 2015
    Inventors: Yoshinori Tokioka, Kenji Tokami, Shintaro Mori, Shigeki Nakamura
  • Publication number: 20150180431
    Abstract: Two LPFs are disposed on the output side of a differential amplifier to remove an AC component contained in an output signal output from a first output terminal of the differential amplifier and an AC component contained in an output signal output from a second output terminal of the differential amplifier. The lowpass filter voltage of the output signal output from the first output terminal with the AC component removed is input to one of input terminals of one of two comparators, and the lowpass filter voltage of the output signal output from the second output terminal with the AC component removed is input to one of input terminals of the other comparator.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 25, 2015
    Inventors: TAKAYUKI ABE, KOJI IMAMURA, KAZUTOSHI SATOU, SHIGEKI NAKAMURA
  • Publication number: 20150146064
    Abstract: An image processing apparatus includes: a target position selecting unit to select a pixel position on an input image, as a target position; a candidate line setting unit to set two or more sets of candidate lines including a pixel with a value, in the vicinity of the target position; a weighted-value calculating unit to calculate a weighted value that corresponds to a degree of expectation that the target position and the pixel position on the candidate line are on the same pattern; a direction classifying unit to selectively determine a set of candidate lines that are close to a direction of a pattern of the target position in accordance with the weighted value of each pixel on the candidate lines; and a first interpolated-value calculating unit to calculate a pixel value of the target position in accordance with the weighted value of each pixel on the candidate lines.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: Shigeki Nakamura, Yasunobu Hitomi, Tomoo Mitsunaga
  • Publication number: 20150097601
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Shigeki NAKAMURA, Shintaro MORI, Yoshinori TOKIOKA, Kenji TOKAMI
  • Patent number: 8994410
    Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Tokioka, Kenji Tokami, Shintaro Mori, Shigeki Nakamura
  • Publication number: 20150084697
    Abstract: An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary.
    Type: Application
    Filed: February 7, 2014
    Publication date: March 26, 2015
    Inventors: Kouji Takahashi, Shigeki Nakamura
  • Patent number: 8941421
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Nakamura, Shintaro Mori, Yoshinori Tokioka, Kenji Tokami
  • Publication number: 20140084972
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki NAKAMURA, Shintaro MORI, Yoshinori TOKIOKA, Kenji TOKAMI
  • Publication number: 20140084983
    Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinori Tokioka, Kenji Tokami, Shintaro Mori, Shigeki Nakamura
  • Publication number: 20140053826
    Abstract: A radiant tube formed of a heat resistant metal includes at least one bent tube (3A (3C)) which connects straight tubes (2A, 2B (2C, 2D)) to each other. Combustion gas from a burner 5 is fed through one of the straight tubes (2A, 2B (2C, 2D)). The radiant tube is characterized in that at least as the bent tube 3A (3C) located closest to the burner 5, there is employed a cast body having an outer diameter ranging from 150 to 210 mm and a wall thickness ranging from 3 to 8 mm.
    Type: Application
    Filed: March 28, 2012
    Publication date: February 27, 2014
    Applicant: KUBOTA CORPORATION
    Inventors: Makoto Hineno, Nobuyuki Sakamoto, Hiroaki Okano, Shigeki Nakamura
  • Patent number: 8422823
    Abstract: An information processing apparatus comprises a data conversion unit for converting second 3D image information, to which first image information can be pasted, into 3D photo frame data including three-dimensional object information representing a three-dimensional shape of an object included in the second 3D image information and parameter information including a pasting position of the first image information, a parse calculation unit for calculating an image of the 3D photo frame data projected onto a display screen, an image pasting unit for pasting the first image information to the 3D photo frame data, and a display control unit for outputting to the display screen the 3D photo frame data or the 3D photo frame data pasted with the first image information.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: April 16, 2013
    Assignee: Sony Corporation
    Inventors: Shunsuke Aoki, Keigo Ihara, Shigeki Nakamura
  • Patent number: 7970137
    Abstract: Content reproduction apparatus, content recording apparatus, network system, and method of recording and reproducing content are provide.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: June 28, 2011
    Assignee: Sony Corporation
    Inventor: Shigeki Nakamura
  • Patent number: 7899420
    Abstract: A wireless transmission device includes a RF power amplification section for amplifying a transmit RF signal and outputting the amplified signal to a transmission antenna, a detector section, and a control section. The RF power amplification section includes a plurality of stages of amplification, the transmit RF signal is input to an input of a first one of the plurality of stages of amplification, and an output of a last one of the plurality of stages of amplification is output to the transmission antenna. The detector section includes a plurality of detectors provided so as to correspond to the plurality of stages of amplification, each for detecting an input level of a corresponding one of the stages of amplification, and a synthesizer for synthesizing together detection outputs from the plurality of detectors. The control section controls, in a feedback control, an output level of the RF power amplification section based on an output level of the synthesizer.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: March 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Shigeki Nakamura, Fumiya Kamimura, Junji Ito, Hidefumi Suzaki
  • Patent number: 7701236
    Abstract: A prove apparatus includes a first and a second loading port for mounting therein two carriers facing each other, a wafer transfer mechanism having a rotation center between the loading ports, and a first and a second inspection unit being symmetrical to each other and disposed in accordance with the arrangement of the loading ports. In this configuration, wafers are directly transferred between the carrier and a wafer chuck of the inspection unit by the wafer transfer mechanism. The wafer transfer mechanism has three arms for unloading two wafers from the carrier. The prove apparatus has a compact size and achieves a high throughput.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: April 20, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Akiyama, Tadashi Obikane, Masaru Suzuki, Yasuhito Yamamoto, Kazuya Yano, Yuji Asakawa, Kazumi Yamagata, Shigeki Nakamura, Eiichi Matsuzawa, Kazuhiro Ozawa, Fumito Kagami, Shinji Kojima
  • Publication number: 20100092105
    Abstract: An information processing apparatus comprises a data conversion unit for converting second 3D image information, to which first image information can be pasted, into 3D photo frame data including three-dimensional object information representing a three-dimensional shape of an object included in the second 3D image information and parameter information including a pasting position of the first image information, a parse calculation unit for calculating an image of the 3D photo frame data projected onto a display screen, an image pasting unit for pasting the first image information to the 3D photo frame data, and a display control unit for outputting to the display screen the 3D photo frame data or the 3D photo frame data pasted with the first image information.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 15, 2010
    Applicant: Sony Corporation
    Inventors: Shunsuke Aoki, Keigo Ihara, Shigeki Nakamura
  • Patent number: 7683712
    Abstract: A differential amplifier circuit is connected to the input node and the output node of the final amplification stage through detection circuits. The signal level difference output from the differential amplifier circuit does not change even if the input power varies. Because a change in the power gain at the output node does not travel back to the input node when the load impedance of the wireless frequency power amplifier varies, it is possible to detect only the change in the load impedance. Damage to the final stage can be prevented by controlling the operating current of the final stage and the gain of the drive stage according to the detected load variation. Nonlinear distortion in the wireless frequency power amplifier output can also be reduced by detecting and canceling the change in the gain of the drive stage by changing the gain of the adjustment stage.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Hidefumi Suzaki, Junji Ito, Fumiya Kamimura, Shigeki Nakamura
  • Patent number: 7576612
    Abstract: The present invention provides a power amplifier that includes the following: an RF operation transistor 3 having a base to which an RF signals is inputted, an emitter connected to the ground, and a collector connected to a power supply and a terminal for outputting an RF signal; a current reference transistor 12 having a collector connected to a reference current source 11, an emitter connected to the ground, and a base connected to the base of the RF operation transistor, an operational amplifier 22 formed of CMOS having one input connected to the collector of the current reference transistor and the other input connected to the base of the RF operation transistor; and a voltage-to-current conversion transistor 22 for converting the output of the operational amplifier 22 into a current to be supplied to the base of the RF operation transistor.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: August 18, 2009
    Assignee: Panasonic Corporation
    Inventors: Shigeki Nakamura, Junji Ito
  • Publication number: 20090011727
    Abstract: A wireless transmission device includes a RF power amplification section for amplifying a transmit RF signal and outputting the amplified signal to a transmission antenna, a detector section, and a control section. The RF power amplification section includes a plurality of stages of amplification, the transmit RF signal is input to an input of a first one of the plurality of stages of amplification, and an output of a last one of the plurality of stages of amplification is output to the transmission antenna. The detector section includes a plurality of detectors provided so as to correspond to the plurality of stages of amplification, each for detecting an input level of a corresponding one of the stages of amplification, and a synthesizer for synthesizing together detection outputs from the plurality of detectors. The control section controls, in a feedback control, an output level of the RF power amplification section based on an output level of the synthesizer.
    Type: Application
    Filed: January 15, 2008
    Publication date: January 8, 2009
    Inventors: Shigeki Nakamura, Fumiya Kamimura, Junji Ito, Hidefumi Suzaki
  • Patent number: D698707
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 4, 2014
    Assignee: Mazda Motor Corporation
    Inventors: Shigeki Nakamura, Kenichi Kuwahara
  • Patent number: D740727
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 13, 2015
    Assignee: Mazda Motor Corporation
    Inventors: Shigeki Nakamura, Atushi Syudou, Yorihiro Murakami, Yasuyuki Murata