Patents by Inventor Shigeki Sako

Shigeki Sako has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5561324
    Abstract: The present invention relates to a semiconductor device which comprises a semiconductor chip mounting section having a through hole, a radiating plate attached to one surface of the semiconductor chip mounting section so as to cover the through hole of the semiconductor chip mounting section, a semiconductor chip mounting plate which is formed within the through hole and mounted on the radiating plate, a surface of the semiconductor chip mounting plate, which is opposite to another surface thereof mounted on the radiating plate, being plated with gold, and the semiconductor chip mounting plate having improved electrical insulation properties and high thermal conductivity, and a semiconductor chip formed within the through hole and attached to the semiconductor chip mounting plate by a conductive adhesive.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kozono, Shigeki Sako, Hiromichi Sawaya
  • Patent number: 5317194
    Abstract: The present invention relates to a semiconductor device sealed by a resin and, more particularly, to a semiconductor device for reducing a production cost and effectively radiating heat generated from a semiconductor element. For this reason, a silicon chip in which an insulating layer is formed between the surface of the silicon chip and a conductive layer is arranged between a heat sink and a semiconductor element. The silicon chip insulates the semiconductor element from the heat sink and transmits heat generated from the semiconductor element to the heat sink. The silicon chip can be manufactured in a line for manufacturing the semiconductor element, and the silicon chip can be assembled with the semiconductor element.
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: May 31, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeki Sako
  • Patent number: 5245216
    Abstract: A plastic-molded type semiconductor device according to the present invention has two islands, on which semiconductor elements are mounted. An insulating circuit board is formed so as to extend over the two islands. On the insulating circuit board, wires are formed. Resin is molded so as to cover the two islands and insulating circuit board. The insulating circuit board overlaps the two islands only at its edges, so that there exists no island just below the insulating circuit board. This reduces the island area and makes it harder for resin cracks to occur, compared with a conventional equivalent.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: September 14, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeki Sako
  • Patent number: 5049977
    Abstract: A plurality of leads and two islands are arranged on a lead frame made of a conductive metal. Semiconductor chips, substrates of which have different thicknesses, are mounted on the two islands, and the lead frame is bent and formed such that the chip mounting surfaces of both the islands are lower than the upper surfaces of the corresponding leads by different amounts.
    Type: Grant
    Filed: July 12, 1990
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeki Sako
  • Patent number: 4984065
    Abstract: A hybrid semiconductor device comprises a heat sink on which a plurality of semiconductor chips are mounted, an insulating substrate secured to the heat sink, conductive metallic layers formed on the insulating substrate, electrodes formed on the semiconductor chips, first thin metallic wires for connecting the electrodes and the conductive metallic layers together, conductive intermediate members integrally formed with the heat sink and located higher than the heat sink, second thin metallic wires for connecting the conductive intermediate members to points to which the first thin metallic wires are connected, and a molding member for sealing and securing the above-mentioned elements. With the above structure, jumpers are arranged in such a manner as not to short-circuit to the conductive metallic layers and other conductive members. Moreover, the hybrid semiconductor device can be manufactured at a low cost since its manufacturing process can reduce the number of steps.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: January 8, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeki Sako
  • Patent number: 4942456
    Abstract: A plastic packaged device comprises a chip element mounted on a supporting member, and covered by a hollow portion. The supporting member has a wall portion at least partially surrounding the chip element. As the hollow portion ends at the wall portion, sufficient space for covering the chip element is achieved.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: July 17, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeki Sako
  • Patent number: D473199
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: April 15, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Sako, Masahiro Ootomo, Kazuyoshi Fukuda, Takahiro Ide
  • Patent number: D480371
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: October 7, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Sako, Masahiro Ootomo, Kazuyoshi Fukuda, Takahiro Ide