Abstract: To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature. A signature verification unit performs signature verification by using the public key and the signature acquired by the acquiring unit, before the program acquired by the acquiring unit is booted. A calculation unit calculates a first MAC value by using a device eigenvalue and stores the first MAC value, when the result of signature verification by the signature verification unit is appropriate. A boot unit calculates a second MAC value by using the device eigenvalue, compares the second MAC value and the stored first MAC value with each other to determine that the program is legitimate, and executes boot based on the determination result.

Abstract: To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature. A signature verification unit performs signature verification by using the public key and the signature acquired by the acquiring unit, before the program acquired by the acquiring unit is booted. A calculation unit calculates a first MAC value by using a device eigenvalue and stores the first MAC value, when the result of signature verification by the signature verification unit is appropriate. A boot unit calculates a second MAC value by using the device eigenvalue, compares the second MAC value and the stored first MAC value with each other to determine that the program is legitimate, and executes boot based on the determination result.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding/decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.

Abstract: A microcomputer and memory control method for the same can reduce the number of parts, cost, and the total surface area required to mount the parts, and thus miniaturize the device in which the microcomputer is incorporated. A microcomputer with a CPU and memory storing a program executed by the CPU comprises a block access nonvolatile memory for storing the program; at least one random access memory unit for temporarily storing an externally input program; and reads the program stored in the block access nonvolatile memory and stores the program in the random access memory as a program sequentially read and executed by the CPU.

Abstract: A semiconductor memory unit which includes a plurality of nonvolatile memories for storing data and is operable at a plurality of source voltages, comprising: a voltage detector for detecting an input voltage inputted to the semiconductor memory unit from the source voltages; and a central processing unit (CPU) which sets a maximum permissible current consumption value of the semiconductor memory unit on the basis of the input voltage and controls the number of the nonvolatile memories operated at a time such that a current consumption value of the semiconductor memory unit does not exceed the maximum permissible current consumption value.

Abstract: A semiconductor memory unit which includes a plurality of nonvolatile memories for storing data and is operable at a plurality of source voltages, comprising: a voltage detector for detecting an input voltage inputted to the semiconductor memory unit from the source voltages; and a central processing unit (CPU) which sets a maximum permissible current consumption value of the semiconductor memory unit on the basis of the input voltage and controls the number of the nonvolatile memories operated at a time such that a current consumption value of the semiconductor memory unit does not exceed the maximum permissible current consumption value.

Abstract: A semiconductor storage device comprises a flash memory and manages the sectors in the unit of groups each consisting of n sectors. A logical sector number is converted to a logical group number and an offset address, and a conversion table is provided to convert a logical group number to a physical group number. A logical sector number is divided with n to get a quotient and a remainder which are set as a logical group number and as an offset address. An access controller determines a physical group number corresponding to the logical group number with reference to the address conversion table, and it accesses a sector in correspondence to the offset address in the physical group number. Further, a group management information for each group is stored in a memory, and when a sector of a logical sector number is accessed, a physical group number of a group storing the data of the sector is traced by referring the conversion table and the group management information.

Abstract: A microcomputer and memory control method for the same can reduce the number of parts, cost, and the total surface area required to mount the parts, and thus miniaturize the device in which the microcomputer is incorporated. A microcomputer with a CPU and memory storing a program executed by the CPU comprises a block access nonvolatile memory for storing the program; at least one random access memory unit for temporarily storing an externally input program; and reads the program stored in the block access nonvolatile memory and stores the program in the random access memory as a program sequentially read and executed by the CPU.

Abstract: A RAM (12) used by the CPU comprises a work buffer (14) and a work register (151) for pipelined processing. The work buffer (14) consists of the first to fourth work buffers (141 to 144) each of which stores information on predetermined data, e.g., a current processing on the data. When the CPU accesses the first to fourth work buffers (141 to 144), an address decoder performs an address conversion on the basis of a value (R151) of the work register (151). For example, when the value (R151) of the work register (151) is “1”, addresses (P1, P2, P3 and P4) in an address space are converted (mapped) to addresses (AD141, AD142, AD143 and AD144) of work buffers (141, 142, 143 and 144). With this constitution, in performing a plurality of data processings in parallel, the CPU can improve its operation efficiency while controlling a currently performed processing on each data.

Abstract: A semiconductor storage device comprises a flash memory and manages the sectors in the unit of groups each consisting of n sectors. A logical sector number is converted to a logical group number and an offset address, and a conversion table is provided to convert a physical group number to a logical group number. A logical sector number is divided with n to get a quotient and a remainder which are set as a logical number and as an offset address. An access controller determines a physical group number corresponding to the logical group number with reference to the address conversion table, and it accesses a sector in correspondence to the offset address in the physical group number. Further, a group management information for each group is stored in a memory, and when a sector of a logical sector number is accessed, a physical group number of a group storing the data of the sector is traced by referring the conversion table and the group management information.