Patents by Inventor Shigeo Kouzuki
Shigeo Kouzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7994006Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: GrantFiled: November 14, 2008Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7564107Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.Type: GrantFiled: September 9, 2004Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
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Publication number: 20090075433Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: ApplicationFiled: November 14, 2008Publication date: March 19, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7462541Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminating portion side.Type: GrantFiled: October 17, 2005Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7423315Abstract: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided bType: GrantFiled: November 3, 2005Date of Patent: September 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Satoshi Taji, Kenichi Tokano
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Patent number: 7341900Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.Type: GrantFiled: July 22, 2005Date of Patent: March 11, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Patent number: 7301202Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: GrantFiled: June 14, 2005Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Patent number: 7262477Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.Type: GrantFiled: October 29, 2003Date of Patent: August 28, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiro Osawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Patent number: 7259426Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.Type: GrantFiled: March 31, 2005Date of Patent: August 21, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7253507Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.Type: GrantFiled: October 29, 2004Date of Patent: August 7, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Satoshi Aida, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7226841Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.Type: GrantFiled: February 18, 2005Date of Patent: June 5, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama
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Patent number: 7224022Abstract: As and B are implanted to side surfaces of trenches 3 by a rotation ion implanting method, and by using a difference between these impurities in diffusion coefficient, the structure in which an n?-type epitaxial Si layer is interposed between trenches 3 is converted into a semiconductor structure consisting of n-type pillar layer 5/p-type pillar layer 4/n-type pillar layer 5 lining up. The structure can function substantially the same role as that of a super junction structure.Type: GrantFiled: March 19, 2004Date of Patent: May 29, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Keinichi Tokano, Yoshihiko Saito, Shigeo Kouzuki, Yasunori Usui, Masaru Izumisawa, Takahiro Kawano
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Publication number: 20060138536Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: ApplicationFiled: June 14, 2005Publication date: June 29, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Publication number: 20060108600Abstract: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided bType: ApplicationFiled: November 3, 2005Publication date: May 25, 2006Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Satoshi Taji, Kenichi Tokano
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Publication number: 20060097313Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar layer of a second conductivity type provided adjacent to the first semiconductor pillar layer; a semiconductor region of the first conductivity type provided between the semiconductor layer and the second semiconductor pillar layer, the semiconductor region having a lower impurity concentration than the semiconductor layer; a semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a semiconductor source region of the first conductivity type selectively provided in the surface of the semiconductor base layer; a gate insulating film provided on the semiconductor base layer between the semiconductor source region and the first semiconductor pillar layer; and a gate electrode provided on the gate insulating film.Type: ApplicationFiled: February 22, 2005Publication date: May 11, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7034346Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.Type: GrantFiled: May 28, 2003Date of Patent: April 25, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Publication number: 20060049459Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviatesType: ApplicationFiled: October 17, 2005Publication date: March 9, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20060017096Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.Type: ApplicationFiled: September 9, 2004Publication date: January 26, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
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Patent number: 6972460Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: GrantFiled: October 8, 2003Date of Patent: December 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20050258503Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.Type: ApplicationFiled: July 22, 2005Publication date: November 24, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa