Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.

Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first co

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviates

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a vertical unit cell and a separating member. The unit cell includes a second conductivity type semiconductor layer and two first conductivity type semiconductor layers to interpose the second conductivity type semiconductor layer from both side surfaces. A pn junction boundary between the second and first conductivity type semiconductor layer is substantially vertical to the main surface of the semiconductor substrate. A second conductivity type base layer on an upper surface of the second conductivity type semiconductor layer has an impurity concentration higher than the second conductivity type semiconductor layer. A first conductivity type source diffusion layer is on a surface of the base layer. A gate insulating film is formed on the base layer interposed between the source diffusion layer and the first conductivity type semiconductor layer. A gate electrode is formed on the gate insulating film.

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first co

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.

Abstract: A semiconductor device includes a semiconductor circuit which is formed inside; and an electrode structure which is formed on a first surface thereof. The electrode structure has a first electrode layer and a metal plating layer. The first electrode layer is formed of a first metal and is connected to the semiconductor circuit. The metal plating layer is formed of a second metal on the first electrode layer. The second metal is capable of being soldered on an extraction electrode outside of the semiconductor device.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type juxtaposed on a semiconductor substrate of the first conductivity type. The first semiconductor layer has an impurity concentration lower than that of the semiconductor substrate. The second semiconductor layer has at a central location a trench, which extends from the upper end toward the semiconductor substrate. A first region of the second conductivity type is formed to include an upper portion of the second semiconductor layer. A second region of the first conductivity type is formed in a surface of the first region. A gate electrode is disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the first semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.