Patents by Inventor Shigeo Kusunoki

Shigeo Kusunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6677821
    Abstract: A circuit that compensates for distortion of an output signal of a power amplifying circuit of a transmitting section of a base station or a terminal of a radio communication system and apparatus such as a mobile phone, and a predistorter system applicable to radio communication systems and that does not depend on a use system other than generation of envelope change due to a high-frequency input signal without addition of the distortion compensating circuit to a base band portion, the compensating circuit including a memory device where inverted distortion data of a high-frequency power amplifying device for a mobile phone are stored is driven with data obtained by detecting an envelope of a high-frequency input signal having envelope change as an address and distortion compensation of the power amplifying device is made by adjusting a variable gain device provided at a prestage of the power amplifying device.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: January 13, 2004
    Assignee: Sony Corporation
    Inventors: Shigeo Kusunoki, Katsuya Yamamoto
  • Patent number: 6556079
    Abstract: A distortion compensating device which can significantly remove residual distortion, in which a value of matching circuit 11 is set up so that the distortion generated at a gain controlling unit 9 offsets the distortion remaining in a power amplifier 12. That is, the value of the matching circuit 11 is set up so that the phase of the residual distortion included in the output of the matching circuit 11 is rendered opposite to the phase of the residual distortion included in the output of the power amplifier 12. Thus, the residual distortion included in the output of the power amplifier 12 is offset by the residual distortion included in the output of the gain controlling unit 9, thereby the residual distortion can be removed.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: April 29, 2003
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 6531917
    Abstract: When distortion is compensated by a predistorter method, the distortion can satisfactorily be compensated by a simple arrangement performing a limit operation in such a manner that when a generated predistortion signal is held at a value smaller than a first level, this predistortion signal is not added to an input signal and that when a generated predistortion signal is held at a value larger than a second level, which is larger than the first level, this predistortion signal is added to an input signal as a predetermined fixed value.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: March 11, 2003
    Assignee: Sony Corporation
    Inventors: Katsuya Yamamoto, Shigeo Kusunoki
  • Publication number: 20020171481
    Abstract: In a high-frequency amplifier circuit, a power detector detects input power, an A/D converter converts the detection output into a digital signal, and then a digital LPF averages the digital signal to obtain data of the average value of input power level. Control data corresponding to the data of the average value is supplied as a control voltage from a DC-to-DC converter controlling memory to a DC-to-DC converter via a D/A means. Thus, a low output voltage Vdd is supplied from the DC-to-DC converter to a power amplifier as circuit supply voltage of the power amplifier at the times of medium and low output power to control unnecessary current consumption by the power amplifier and thereby increase efficiency of the power amplifier at the times of medium and low output power.
    Type: Application
    Filed: April 9, 2002
    Publication date: November 21, 2002
    Inventors: Noboru Sasho, Shigeo Kusunoki, Masayoshi Abe
  • Patent number: 6480705
    Abstract: An apparatus and method for distortion compensation of a high frequency power amplification section wherein a finite difference between envelopes of input and output signals of an amplifier of an object of distortion compensation is detected, and variation of a temperature and other parameters is suppressed using a component which originates from an offset of the finite difference. Further, a component of the finite difference which originates from the distortion is added to the input signal of the amplifier to effect distortion compensation.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: November 12, 2002
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Publication number: 20020153950
    Abstract: The present invention relates to a distortion compensating circuit which compensates for non-linear distortion of an output signal of a power amplifying circuit to be used for a transmitting section of a base station or a terminal station of a radio communication system and a radio communication apparatus such as a mobile phone, and more particularly, to improvement of predistorter system widely applicable to a variety of radio communication systems, which does not depend on a use system other than generation of envelope change due to a high frequency input signal without addition of the distortion compensating circuit to a base band portion, and to the distortion compensating circuit in which a memory means 3 where inverted distortion data of a high frequency power amplifying means 12 for a mobile phone or the like is stored in advance is driven with digitalized data obtained by detecting an envelope of a high frequency input signal having envelope change as an address and distortion compensation of the high
    Type: Application
    Filed: May 28, 2002
    Publication date: October 24, 2002
    Inventors: Shigeo Kusunoki, Katsuya Yamamoto
  • Patent number: 6466092
    Abstract: A distortion compensation method and apparatus for compensating distortion components of a device, such as a power amplifier, wherein should distortion persist in an output of the power amplifier 23, only distortion components are represented on subtracted results S40. These subtracted results S40 are summed to data written in a random access memory 17 with a signal S3 as an address, and are again written in a second memory 17. The data in the random access memory 17 provide an address for a next following third memory 19 to help output data S44 stored in the third memory 19. These data S44 in the third memory are summed by an adder 7 provided in an amplitude distortion correction channel to amplitude correct data in the first memory 6. The resulting sum data is input to the power amplifier 23 desired to be compensated to contribute to correction of the amplitude distortion.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: October 15, 2002
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 6452447
    Abstract: An adaptive distortion-compensation apparatus that can perform conversion of the output of a power amplifier to a base band signal without using an orthogonal demodulator is constructed of first envelope detection means DET1 that has input thereto a high-frequency input signal whose envelope fluctuates and from that there is obtained first envelope detection signal, a read/write storage RAM1 that has supplied thereto an address signal based on the first envelope detection signal to have read out therefrom an output data signal and that has written therein a write data signal, a latch LCH that latches an output data signal that has been read out from the storage RAM1, a second envelope detection DET2 that has supplied thereto an output signal of a power amplifier the distortion of which is to be compensated and that has obtained therefrom a second envelope detection signal, and a difference sign detection/logical converter that outputs a digital value corresponding to the difference between the first and the s
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: September 17, 2002
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Publication number: 20020079963
    Abstract: Providing a distortion compensating device which can significantly remove residual distortion. The value of the matching circuit 11 is set up so that the distortion generated at the gain controlling unit 9 offsets the distortion remaining in the power amplifier 12. That is, the value of the matching circuit 11 is set up so that the phase of the residual distortion included in the output of the matching circuit 11 is rendered opposite to the phase of the residual distortion included in the output of the power amplifier 12. Thus, the residual distortion included in the output of the power amplifier 12 is offset by the residual distortion included in the output of the gain controlling unit 9, thereby the residual distortion can be removed.
    Type: Application
    Filed: September 26, 2001
    Publication date: June 27, 2002
    Inventor: Shigeo Kusunoki
  • Publication number: 20020061074
    Abstract: In the present invention, distortion component of a device such as a power amplifier can be easily compensated for, and a simple structure can be achieved without requiring a demodulator. A voltage comparator (17) compares an envelope voltage of an output PA_out of a power amplifier (14), which has been corrected by an AM_ct1 signal outputted from an amplitude correction memory (4), with an envelope voltage before the correction, to detect which of the envelope voltages is larger/smaller. Further, a logic section (18) adds and/or subtracts data in an amplitude compensation memory, so as to correct the relationship as to which of the envelope voltages is larger/smaller. At this time, data in the memory is updated by one bit for every one time of operation. Therefore, the data is corrected to a correct value by accessing one same address sometimes.
    Type: Application
    Filed: September 26, 2001
    Publication date: May 23, 2002
    Inventor: Shigeo Kusunoki
  • Patent number: 6393259
    Abstract: In an amplifier circuit and a transceiver, inter-modulation distortion caused by a transmission signal (S17) leaking from a transmission circuit (11) is eliminated without increasing the current output from the output terminal of an amplification element. An adjustment circuit constituted by connecting a phase rotation element (SL) and a resistive element (Rf) in series is connected between the input terminal and the output terminal of the amplification element (Q) and the rotation angle of the phase rotation element and the resistance value of the resistive element are set to desired values respectively. Therefore, it is possible to reduce inter-modulation distortion while preventing current consumption from increasing and thus, to prevent the reception sensitivity from deteriorating without increasing power consumption.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: May 21, 2002
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Publication number: 20020021173
    Abstract: When a distortion is compensated by a predistorter method, a distortion can satisfactorily be compensated by a simple arrangement. A limit operation can be made in such a manner that when a generated predistortion signal is held at a value smaller than a first level, this predistortion signal is not added to an input signal and that when a generated predistortion signal is held at a value larger than a second level which is larger than the first level, this predistortion signal is added to an input signal as a predetermined fixed value.
    Type: Application
    Filed: June 7, 2001
    Publication date: February 21, 2002
    Inventors: Katsuya Yamamoto, Shigeo Kusunoki
  • Publication number: 20020009979
    Abstract: To provide a distortion-compensating apparatus capable of stably determining update values when distortion-compensating data to be stored in an amplitude(gain)-compensation-data memory is updated corresponding to ambient temperatures in a distortion-compensating apparatus of an RF-power amplifying means. When updating adverse distortion data for an RF-power amplifying means 12 in a portable telephone or the like corresponding to ambient temperatures, envelope detection signals at input and output sides of the power amplifying means 12, the distortion-compensating apparatus digitizes the individual envelope signals, performs arithmetic operations to obtain the amount of a deviation from a linear gain by using arithmetic-operation means 20 and 21, and thereby updates adverse distortion data to be stored in amplitude-compensation-data memory 7, 7a, 7b.
    Type: Application
    Filed: May 1, 2001
    Publication date: January 24, 2002
    Inventor: Shigeo Kusunoki
  • Publication number: 20020010567
    Abstract: A distortion compensation method and apparatus for compensating distortion components of a device, such as a power amplifier, extremely readily. Should distortion persist in an output of a power amplifier 23, desired to be compensated, only distortion components are represented on subtracted results S40. These subtracted results S40 are summed to data written in a random access memory 17 with a signal S3 as an address, and are agin written in a random access memory 17. The data in the random access memory 17 prove an address for a next following third memory 19 to help output data S44 stored in the third memory 19. These data S44 in the third memory are summed by a second adder 7 provided in an amplitude distortion correction channel to amplitude correction data in the first memory 6. The resulting sum data is input to the power amplifier 23 desired to be compensated to contribute to correction of the amplitude distortion.
    Type: Application
    Filed: June 15, 2001
    Publication date: January 24, 2002
    Inventor: Shigeo Kusunoki
  • Publication number: 20020000881
    Abstract: To provide an adaptive distortion-compensation apparatus that can perform conversion of the output of a power amplifier to a base band signal without using an orthogonal demodulator.
    Type: Application
    Filed: June 26, 2001
    Publication date: January 3, 2002
    Inventor: Shigeo Kusunoki
  • Patent number: 6201455
    Abstract: An antenna switch circuit which suppresses production of a cross modulation distortion includes an input terminal and an output terminal, a field effect transistor connected at a first one of a source electrode and a drain electrode thereof to the input terminal and connected at a second one of the source electrode and the drain electrode to the output terminal, a first controlling power supply to which the drain electrode and the source electrode of the field effect transistor are connected through first and second biasing elements, respectively, a second controlling power supply to which a gate electrode of the field effect transistor is connected through a third biasing element, and a phase shifting element and a feedback resistor connected in series between the second electrode and the gate electrode of the field effect transistor. The field effect transistor is controlled between on and off by varying a voltage of at least one of the first and second controlling power supplies.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: March 13, 2001
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 5963089
    Abstract: A semiconductor amplifying apparatus and a communication terminal apparatus to satisfy a standard value for adjacent channel power and amplify the power at a high efficiency. The value of an impedance viewed from an input terminal side of an impedance circuit network connected to an input terminal of a transistor is set at a value which causes a characteristic curve for a mutual modulation distortion component included in output power of the transistor to form, in the middle thereof, a curve section in which an inclination angle of a tangential line to this characteristic curve once becomes smaller, or a curve section which protrudes downwardly.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: October 5, 1999
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 5781071
    Abstract: A transformer and an amplifier exhibiting a small lowering in self resonance frequency and having a large mutual inductance. By forming a first flat coil 12A, 31C, 86A, 96A, 102A on the semiconductor substrate surface 11A with the pattern wiring of any conductor and forming a second flat coil 12A, 31A, 31B, 86B, 96B, 102A, 102B along the pattern wiring of the first flat coil 12A, 31C, 86A, 96A, 102A on the insulator layer surface 13A spaced by an insulator layer having a predetermined thickness with the pattern wiring of any conductor, a large mutual conductance can be obtained and further a power amplification based on the class-B push-pull operation can be carried out by forming an amplifier 45, 75, 81 with the aid of a 5-terminal first output transformer 30.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: July 14, 1998
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 5471656
    Abstract: A communication apparatus is small in power consumption and suitable for use in a portable radio communication apparatus. The communication apparatus includes a semiconductor power amplifier integrated circuit which uses a GaAs junction type FET having a gate bias terminal to which a gate bias voltage is applied. The integrated circuit decreases its amount of power consumption in a manner that the integrated circuit is operated to perform an amplification operation during a communication operation and not operated when a communication is interrupted or a time slot is not allotted to the communication apparatus itself. A detector detects a portion of a high-frequency signal to the amplifier circuit to provide an input to a gate bias generator which provides an input to an adder circuit, the output of which controls the bias on the power amplifier.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: November 28, 1995
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki
  • Patent number: 5408198
    Abstract: A power amplifier is provided which operates in a quasi-microwave band between 0.8 GHz and 2 GHz with a high output, a small size and low power consumption. Junction type GaAs FETs are connected in a multi-stage manner to form an amplification circuit. An impedance matching/phase adjusting circuit is provided between the respective stages. An input impedance matching circuit, an output impedance matching circuit and bypass capacitors for a power source terminal are provided. Further, a gain control terminal and gate bias terminals for setting operating points of the JFETs are provided, thereby forming an entire arrangement as a semiconductor integrated circuit.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: April 18, 1995
    Assignee: Sony Corporation
    Inventor: Shigeo Kusunoki