Abstract: A data transfer controlling device is mounted in an IC card having: a communication device for data communication with an external device; a memory device for storing data received from and transmitted to the external device; and an operation processing device for controlling the memory device and the communication device, and controls a data transfer process. The controlling device comprises: a status information acquiring section for acquiring status information including at least error detection information from the communication device; a determination section for determining whether or not the data transfer process can be executed based on the status information acquired by the status information acquiring section when the data transfer process is being executed; and a data transfer process executing section for executing the data transfer process in accordance with a result of determination as to whether or not the data transfer process can be executed by the determination section.

Abstract: An IC card (1) includes: a plurality of circuit blocks (11 to 14); and an internal bus (21) which allows the circuit blocks to be connected to one another. Out of the circuit blocks, a CPU block (11) on an output side includes an encoding circuit (41) for outputting data to be transferred to a signal line (21a) of the data bus (22) after encoding the data in accordance with a predetermined encoding method so that variation of the data is evener, and a coprocessor block (12) on an input side includes a decoding circuit (42) for decoding the encoded data transferred via the signal line (21a). As a result, it is possible to realize (i) a semiconductor device which includes the plural circuit blocks and the internal signal line which allows the circuit blocks to be connected to one another but can decrease a possibility that data transferred among the circuit blocks may be estimated by power consumption analysis and (ii) an IC card having the semiconductor device.

Abstract: There is a provided a semiconductor device having a high security whose power consumption is difficult to analyze even without setting up random characteristic to the processing time. The semiconductor device includes a target circuit (14), a sub-target circuit (15) having the same circuit configuration as the target circuit (14), and a dummy bit string generation circuit (11) for generating a bit string of a dummy serial input signal to be inputted to the sub-target circuit (15) according to the bit string of the serial input signal of the target circuit (14).

Abstract: A computer system for preventing secret data in a memory area from being erased, altered or leaked due to a buffer overflow attack and the like comprises a memory map circuit for storing an access control memory map which defines whether the CPU has an access right for executing a program with respect to each address of the memory area, an access right determination circuit for determining whether the CPU has the access right to the memory area of an execution program storage address designated by a program counter based on the access control memory map, and outputting an access prohibition signal which makes the CPU execute a predetermined operation to disable the CPU from accessing the memory area of the execution program storage address when the CPU does not have the access right.

Abstract: A secure semiconductor apparatus is provided which can make power consumption analysis difficult without increasing the power consumption at the peak. The apparatus comprises a logic circuit for conducting a logic operation, a power consumption modifying circuit for increasing or decreasing its power consumption to offset the increase or decrease in the power consumption of the logic circuit. The apparatus further comprises an action state control circuit for randomly controlling the starting and stopping of the action of the logic circuit. The action state control circuit randomly stops the action of the logic circuit and when the power consumption of the logic circuit has been declined, the action state control circuit starts the action of the power consumption modifying circuit to increase the power consumption of the power consumption modifying circuit so as to compensate for a declination in the power consumption of the logic circuit.

Abstract: A combination-type IC card is provided with both of (i) a contact-type interface for reading and writing data via contact-type communication terminals provided in a card, and (ii) a non-contact-type communication interface, which includes a non-contact-type communication parallel resonance circuit, for reading and writing data received, via an antenna coil, data transmitted via radio waves. Further, the combination-type IC card is provided with a contact/non-contact judging circuit for judging whether communication is contact-type communication or non-contact communication, by judging from a difference between (i) a frequency of a clock for contact communication, which is inputted via a clock terminal, which is one of the contact-type communication terminals, and (ii) a frequency of a clock for non-contact communication, which is received via the antenna coil.

Abstract: A combination-type IC card is provided with both of (i) a contact-type interface for reading and writing data via contact-type communication terminals provided in a card, and (ii) a non-contact-type communication interface, which includes a non-contact-type communication parallel resonance circuit, for reading and writing data received, via an antenna coil, data transmitted via radio waves. Further, the combination-type IC card is provided with a contact/non-contact judging circuit for judging whether communication is contact-type communication or non-contact communication, by judging from a difference between (i) a frequency of a clock for contact communication, which is inputted via a clock terminal, which is one of the contact-type communication terminals, and (ii) a frequency of a clock for non-contact communication, which is received via the antenna coil.

Abstract: This invention is intended to provide a scrambler circuit capable of realizing a data processing device or an IC card having high security enough to prevent information in a memory or information on a bus from being decrypted. The scrambler circuit has to-be-processed data divided into two data blocks and processed data divided into two data blocks, and includes a first scrambler unit that conducts first scrambling to the data block and that outputs first intermediate data, a first arithmetic unit that performs an exclusive OR operation between the data block and the first intermediate data and that outputs the data block, a second scrambler unit that conducts second scrambling to the data block and that outputs second intermediate data, and a second arithmetic unit that performs an exclusive OR operation between the second intermediate data and the data block and that outputs the data block.