Patents by Inventor Shigeo Tokumitsu
Shigeo Tokumitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881514Abstract: Provided is a highly reliable semiconductor device in which an influence on device characteristics can be reduced while improving a high temperature and high humidity bias resistance of a termination structure (termination region) of a chip by a relatively simple method. The semiconductor device includes an active region disposed on a main surface of a semiconductor substrate, and a termination region disposed on the main surface so as to surround the active region. The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate, and an organic protective film formed so as to cover the interlayer insulating film. An insulating film having a thickness of 100 nm or less and containing nitrogen is provided between the interlayer insulating film and the organic protective film.Type: GrantFiled: November 22, 2021Date of Patent: January 23, 2024Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Shigeo Tokumitsu, Masaki Shiraishi, Yutaka Kato, Tetsuo Oda
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Patent number: 11843036Abstract: Provided is a highly reliable semiconductor device in which an influence on device characteristics can be reduced while improving a high temperature and high humidity bias resistance of a termination structure (termination region) of a chip by a relatively simple method. The semiconductor device includes an active region disposed on a main surface of a semiconductor substrate, and a termination region disposed on the main surface so as to surround the active region. The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate, and an organic protective film formed so as to cover the interlayer insulating film. An insulating film having a thickness of 100 nm or less and containing nitrogen is provided between the interlayer insulating film and the organic protective film.Type: GrantFiled: November 22, 2021Date of Patent: December 12, 2023Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Shigeo Tokumitsu, Masaki Shiraishi, Yutaka Kato, Tetsuo Oda
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Publication number: 20220199786Abstract: Provided is a highly reliable semiconductor device in which an influence on device characteristics can be reduced while improving a high temperature and high humidity bias resistance of a termination structure (termination region) of a chip by a relatively simple method. The semiconductor device includes an active region disposed on a main surface of a semiconductor substrate, and a termination region disposed on the main surface so as to surround the active region. The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate, and an organic protective film formed so as to cover the interlayer insulating film. An insulating film having a thickness of 100 nm or less and containing nitrogen is provided between the interlayer insulating film and the organic protective film.Type: ApplicationFiled: November 22, 2021Publication date: June 23, 2022Applicant: Hitachi Power Semiconductor Device, Ltd.Inventors: Shigeo Tokumitsu, Masaki Shiraishi, Yutaka Kato, Tetsuo Oda
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Patent number: 11289363Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: GrantFiled: May 12, 2020Date of Patent: March 29, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shigeo Tokumitsu, Yoshiki Maruyama, Satoshi Iida
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Publication number: 20200411360Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: ApplicationFiled: May 12, 2020Publication date: December 31, 2020Inventors: Shigeo TOKUMITSU, Yoshiki MARUYAMA, Satoshi IIDA
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Patent number: 10546802Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.Type: GrantFiled: February 28, 2018Date of Patent: January 28, 2020Assignee: Renesas Electronics CorporationInventors: Hiroaki Sekikawa, Shigeo Tokumitsu, Asuka Komuro
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Patent number: 10229909Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.Type: GrantFiled: March 20, 2017Date of Patent: March 12, 2019Assignee: Renesas Electronics CorporationInventors: Shigeo Tokumitsu, Hiroki Fujii
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Publication number: 20180350656Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.Type: ApplicationFiled: July 31, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventors: Masaaki SHINOHARA, Shigeo TOKUMITSU
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Publication number: 20180261530Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.Type: ApplicationFiled: February 28, 2018Publication date: September 13, 2018Inventors: Hiroaki SEKIKAWA, Shigeo TOKUMITSU, Asuka KOMURO
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Patent number: 10074556Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.Type: GrantFiled: June 13, 2016Date of Patent: September 11, 2018Assignee: Renesas Electronics CorporationInventors: Masaaki Shinohara, Shigeo Tokumitsu
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Patent number: 9881868Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: GrantFiled: October 17, 2014Date of Patent: January 30, 2018Assignee: Renesas Electronics CorporationInventors: Shigeo Tokumitsu, Takahiro Mori, Tetsuya Nitta
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Publication number: 20170365553Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: ApplicationFiled: September 6, 2017Publication date: December 21, 2017Applicant: Renesas Electronics CorporationInventors: Shigeo TOKUMITSU, Takahiro MORI, Tetsuya NITTA
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Patent number: 9786594Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.Type: GrantFiled: October 17, 2014Date of Patent: October 10, 2017Assignee: Renesas Electronics CorporationInventors: Shigeo Tokumitsu, Takahiro Mori, Tetsuya Nitta
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Publication number: 20170287912Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.Type: ApplicationFiled: March 20, 2017Publication date: October 5, 2017Applicant: Renesas Electronics CorporationInventors: Shigeo TOKUMITSU, Hiroki FUJII
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Publication number: 20170288013Abstract: A semiconductor device includes a high voltage transistor formation region defined by an element isolation insulating film, a transistor formation region defined by an element isolation insulating film, and a substrate contact portion. A crystal defect region is formed at a portion of a semiconductor substrate that is positioned immediately below each of the substrate contact portion and element isolation insulating films.Type: ApplicationFiled: March 24, 2017Publication date: October 5, 2017Applicant: Renesas Electronics CorporationInventor: Shigeo TOKUMITSU
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Publication number: 20170250107Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: Renesas Electronics CorporationInventor: Shigeo TOKUMITSU
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Patent number: 9691852Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.Type: GrantFiled: May 5, 2015Date of Patent: June 27, 2017Assignee: Renesas Electronics CorporationInventor: Shigeo Tokumitsu
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Publication number: 20170047338Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.Type: ApplicationFiled: June 13, 2016Publication date: February 16, 2017Applicant: Renesas Electronics CorporationInventors: Masaaki SHINOHARA, Shigeo TOKUMITSU
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Publication number: 20150349055Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.Type: ApplicationFiled: May 5, 2015Publication date: December 3, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Shigeo TOKUMITSU
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Publication number: 20150295045Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.Type: ApplicationFiled: June 22, 2015Publication date: October 15, 2015Inventors: Shigeo TOKUMITSU, Akio UENISHI