Patents by Inventor Shigeo Yoshii

Shigeo Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741600
    Abstract: An imaging device including a semiconductor substrate; and a pixel. The pixel includes a photoelectric converter having a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the photoelectric converter located above a surface of the semiconductor substrate; a first transistor that includes a part of the semiconductor substrate and detects electric charges; and a second transistor that includes a gate electrode and initializes a voltage of the first electrode. The first electrode, the second transistor, and the first transistor are arranged in that order toward the semiconductor substrate from the first electrode in cross sectional view, and when viewed from the direction normal to the surface of the semiconductor substrate, a part of the gate electrode overlaps the first electrode, and another part of the gate electrode does not overlap the first electrode.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 11, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tokuhiko Tamaki, Junji Hirase, Shigeo Yoshii
  • Publication number: 20190081099
    Abstract: An imaging device including a semiconductor substrate; and a pixel. The pixel includes a photoelectric converter having a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the photoelectric converter located above a surface of the semiconductor substrate; a first transistor that includes a part of the semiconductor substrate and detects electric charges; and a second transistor that includes a gate electrode and initializes a voltage of the first electrode. The first electrode, the second transistor, and the first transistor are arranged in that order toward the semiconductor substrate from the first electrode in cross sectional view, and when viewed from the direction normal to the surface of the semiconductor substrate, a part of the gate electrode overlaps the first electrode, and another part of the gate electrode does not overlap the first electrode.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Tokuhiko TAMAKI, Junji HIRASE, Shigeo YOSHII
  • Patent number: 10164123
    Abstract: An imaging device includes a semiconductor substrate comprising a first semiconductor; and a unit pixel cell provided to the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes at least a part of a first semiconductor layer comprising a second semiconductor and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. A band gap of the second semiconductor is larger than a band gap of the first semiconductor.
    Type: Grant
    Filed: May 17, 2015
    Date of Patent: December 25, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigeo Yoshii, Junji Hirase, Daisuke Ueda
  • Patent number: 10157952
    Abstract: An imaging device includes a semiconductor substrate and at least one unit pixel cell provided to a surface of the semiconductor substrate. Each of the at least one unit pixel cell includes: a photoelectric converter including a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, at least a part of the gate electrode is located outside the pixel electrode.
    Type: Grant
    Filed: May 17, 2015
    Date of Patent: December 18, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tokuhiko Tamaki, Junji Hirase, Shigeo Yoshii
  • Publication number: 20170084925
    Abstract: A charge storage device includes: a first electrode; a second electrode; a charge storage layer disposed between the first electrode and the second electrode; and an oxide layer disposed between the second electrode and the charge storage layer. The charge storage layer contains a mixture of semiconductor particles and insulator particles. An average particle size of the insulator particles is greater than or equal to the average particle size of the semiconductor particles.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 23, 2017
    Inventors: SHIGEO YOSHII, NORIHITO FUJINOKI, HARUHIKO HABUTA
  • Publication number: 20150340401
    Abstract: An imaging device includes a semiconductor substrate comprising a first semiconductor; and a unit pixel cell provided to the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes at least a part of a first semiconductor layer comprising a second semiconductor and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. A band gap of the second semiconductor is larger than a band gap of the first semiconductor.
    Type: Application
    Filed: May 17, 2015
    Publication date: November 26, 2015
    Inventors: SHIGEO YOSHII, JUNJI HIRASE, DAISUKE UEDA
  • Publication number: 20150340393
    Abstract: An imaging device includes a semiconductor substrate and at least one unit pixel cell provided to a surface of the semiconductor substrate. Each of the at least one unit pixel cell includes: a photoelectric converter including a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, at least a part of the gate electrode is located outside the pixel electrode.
    Type: Application
    Filed: May 17, 2015
    Publication date: November 26, 2015
    Inventors: TOKUHIKO TAMAKI, JUNJI HIRASE, SHIGEO YOSHII
  • Patent number: 8470549
    Abstract: The present invention relates to a method for detecting an antigen with use of an antibody and an enzyme. Specifically, the present invention provides a method for detecting an antigen without use of a labeled-antibody. the method comprises immersing particles in a first buffer solution which is predicted to contain the antigen; wherein an antibody and a multi-copper oxidase CueO are immobilized on each surface of the particles, and the antibody reacts specifically with the antigen. The method further comprises the following steps recovering the obtained particles; mixing the particles recovered, an oxidation-reduction indicator (reductant), and a second buffer solution so as to prepare a reaction solution; measuring an activity degree of the multi-copper oxidase CueO contained in the reaction solution; determining that the first buffer solution contains the antigen based on the above activity degree.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuaki Nishio, Nozomu Matsukawa, Shigeo Yoshii
  • Publication number: 20120309033
    Abstract: The present invention relates to a method for detecting an antigen with use of an antibody and an enzyme. Specifically, the present invention provides a method for detecting an antigen without use of a labeled-antibody. the method comprises immersing particles in a first buffer solution which is predicted to contain the antigen; wherein an antibody and a multi-copper oxidase CueO are immobilized on each surface of the particles, and the antibody reacts specifically with the antigen. The method further comprises the following steps recovering the obtained particles; mixing the particles recovered, an oxidation-reduction indicator (reductant), and a second buffer solution so as to prepare a reaction solution; measuring an activity degree of the multi-copper oxidase CueO contained in the reaction solution; determining that the first buffer solution contains the antigen based on the above activity degree.
    Type: Application
    Filed: June 28, 2012
    Publication date: December 6, 2012
    Applicant: Panasonic Corporation
    Inventors: Kazuaki Nishio, Nozomu Matsukawa, Shigeo Yoshii
  • Patent number: 8309345
    Abstract: Provided is a method for detecting an antigen without use of a labeled-antibody. A support having an antibody and a multi-copper oxidase CueO immobilized thereon is brought into contact with a first buffer solution containing the antigen, a current is measured by a potentiostat method using the support and a second buffer solution, and when the measured current is greater than or equal to 1.5×(blank value), it is determined that the antigen exists. The second buffer solution contains a substrate of the CueO and has an ionic strength falling within a range of not less than 0.3 mM and not more than 1.0 mM.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 13, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazuaki Nishio, Nozomu Matsukawa, Shigeo Yoshii
  • Publication number: 20120058490
    Abstract: Provided is a method for detecting an antigen without use of a labeled-antibody. A support having an antibody and a multi-copper oxidase CueO immobilized thereon is brought into contact with a first buffer solution containing the antigen, a current is measured by a potentiostat method using the support and a second buffer solution, and when the measured current is greater than or equal to 1.5×(blank value), it is determined that the antigen exists. The second buffer solution contains a substrate of the CueO and has an ionic strength falling within a range of not less than 0.3 mM and not more than 1.0 mM.
    Type: Application
    Filed: November 15, 2011
    Publication date: March 8, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuaki NISHIO, Nozomu Matsukawa, Shigeo Yoshii
  • Patent number: 7919596
    Abstract: To provide a method of arranging ferritin by which a high rate of the number of the molecular film spots on which sole ferritin molecule was arranged in effect, with respect to total number of the molecular film spots provided for arranging ferritin (sole arrangement rate) is achieved is objected to. Specifically, in Fer8 ferritin having a sequence excluding 7 amino acids of from the second to the eighth, from an amino acid sequence (Fer0 sequence) translated from a naturally occurring DNA sequence, lysine at position 91 is substituted with glutamic acid.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Shigeo Yoshii, Kazuaki Nishio, Shinya Kumagai, Ichiro Yamashita
  • Patent number: 7738280
    Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Shigeo Yoshii, Ichiro Yamashita
  • Publication number: 20100008128
    Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.
    Type: Application
    Filed: September 2, 2009
    Publication date: January 14, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Shigeo YOSHII, Ichiro YAMASHITA
  • Publication number: 20090187010
    Abstract: To provide a method of arranging ferritin by which a high rate of the number of the molecular film spots on which sole ferritin molecule was arranged in effect, with respect to total number of the molecular film spots provided for arranging ferritin (sole arrangement rate) is achieved is objected to. Specifically, in Fer8 ferritin having a sequence excluding 7 amino acids of from the second to the eighth, from an amino acid sequence (Fer0 sequence) translated from a naturally occurring DNA sequence, lysine at position 91 is substituted with glutamic acid.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 23, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Shigeo Yoshii, Kazuaki Nishio, Shinya Kumagai, Ichiro Yamashita
  • Patent number: 7419529
    Abstract: An object of the present invention is to provide a method of forming fine particles on a substrate in which reoxidization of reduced fine particles is suppressed. Reduced fine particles (FeO fine particles) are formed by embedding metal oxide fine particles (Fe2O3 fine particles) fixed on a p type silicon semiconductor substrate into a silicon oxidized film, and carrying out a heat treatment in a reducing gas atmosphere. Presence of the silicon oxidized film enables suppression of reoxidization of the reduced fine particles (FeO fine particles) due to exposure to the ambient air.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: September 2, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Michihito Ueda, Nozomu Matsukawa, Ichiro Yamashita
  • Patent number: 7419849
    Abstract: The present invention provides a method for production of a single electron semiconductor element (SET) in which a quantum dot is selectively arranged in a nano gap between fine electrodes, whereby the product yield is significantly improved, leading to excellent practical applicability. The method for production of SET of the present invention is characterized in that a solution containing ferritin including a metal or semiconductor particle therein, and a nonionic surfactant is dropped on a substrate having a source electrode and a drain electrode formed by laminating a titanium film and a film of a metal other than titanium, whereby the ferritin is selectively arranged in a nano gap between the source electrode/drain electrode.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: September 2, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Kumagai, Shigeo Yoshii, Nozomu Matsukawa, Ichiro Yamashita
  • Patent number: 7414261
    Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: August 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuyuki Otsuka, Koichi Mizuno, Shigeo Yoshii, Asamira Suzuki
  • Publication number: 20080108227
    Abstract: The present invention provides a method for production of a single electron semiconductor element (SET) in which a quantum dot is selectively arranged in a nano gap between fine electrodes, whereby the product yield is significantly improved, leading to excellent practical applicability. The method for production of SET of the present invention is characterized in that a solution containing ferritin including a metal or semiconductor particle therein, and a nonionic surfactant is dropped on a substrate having a source electrode and a drain electrode formed by laminating a titanium film and a film of a metal other than titanium, whereby the ferritin is selectively arranged in a nano gap between the source electrode/drain electrode.
    Type: Application
    Filed: July 26, 2007
    Publication date: May 8, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinya Kumagai, Shigeo Yoshii, Nozomu Matsukawa, Ichiro Yamashita
  • Patent number: 7323725
    Abstract: The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer disposed between the emitter layer and the base layer; a collector electrode, a base electrode and the emitter layer all connected to an emitter electrode; the quantum dot barrier layer having a plurality of quantum dots being sandwiched between first and second barrier layers from the emitter layer side and the base layer side, respectively and each having a portion that is convex to the base layer; a base layer side interface in the second barrier layer, and collector layer side and emitter layer side interfaces in the base layer having curvatures that are convex to the collector layer corresponding to the convex portions of the quantum dots.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Nobuyuki Otsuka, Koichi Mizuno, Asamira Suzuki