Patents by Inventor Shigeo Yoshii

Shigeo Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030141518
    Abstract: A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple &dgr;-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple &dgr;-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple &dgr;-doped InAlAs layer (204) as a carrier supplying layer is reduced.
    Type: Application
    Filed: January 29, 2003
    Publication date: July 31, 2003
    Inventors: Toshiya Yokogawa, Asamira Suzuki, Masahiro Deguchi, Shigeo Yoshii, Hiroyuki Furuya
  • Publication number: 20030132432
    Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.
    Type: Application
    Filed: January 24, 2003
    Publication date: July 17, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Kiyoshi Morimoto, Kiyoyuki Morita, Haruyuki Sorada
  • Patent number: 6548825
    Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: April 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Kiyoshi Morimoto, Kiyoyuki Morita, Haruyuki Sorada
  • Publication number: 20020142163
    Abstract: The present invention provides aligned fine particles that are aligned on a substrate. An organic coating film is bonded to surfaces of the fine particles is formed on the surfaces of the fine particles. An organic coating film bonded to a surface of the substrate is formed on the surface of the substrate. The organic coating film on the surfaces of the fine particles is bonded to the organic coating film on the surface of the substrate, whereby the fine particles are immobilized and aligned on the substrate. Thus, it is possible to align the fine particles of a nanometer scale in a specific direction. When fine magnetic particles are used, a magnetic recording medium for high recording density can be obtained, and a high-density magnetic recording/reproducing apparatus can be provided.
    Type: Application
    Filed: January 22, 2002
    Publication date: October 3, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Norihisa Mino, Yasuhiro Kawawake, Kiyoyuki Morita, Shigeo Yoshii, Mutuaki Murakami, Osamu Kusumoto
  • Publication number: 20020030195
    Abstract: A semiconductor light-emitting device has first and second semiconductor layers each of a first conductivity type, a third semiconductor layer of a second conductivity type provided between the first and second semiconductor layers, and an active layer provided between the second and third semiconductor layers to emit light with charge injected therein from the second and third semiconductor layers. A graded composition layer is provided between the active layer and the third semiconductor layer to have a varying composition which is nearly equal to the composition of the active layer at the interface with the active layer and to the composition of the third semiconductor layer at the interface with the third semiconductor layer.
    Type: Application
    Filed: July 2, 2001
    Publication date: March 14, 2002
    Inventors: Shigeo Yoshii, Kiyoshi Ohnaka
  • Patent number: 6169296
    Abstract: The light-emitting diode device of the present invention includes an active layer, a p-type contact layer, a Schottky electrode and an ohmic electrode. The active layer is formed over an n-type semiconductor substrate. The contact layer is formed over the active layer. The Schottky electrode is selectively formed on the contact layer and makes Schottky contact with the contact layer. The ohmic electrode is formed to surround the Schottky electrode on the contact layer and to be electrically connected to the Schottky electrode and transmits the light emitted from the active layer.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Kamiyama, Shigeo Yoshii, Ryoko Miyanaga, Takashi Nishikawa, Tohru Saitoh, Yoichi Sasai
  • Patent number: 6087725
    Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Yoichi Sasai, Satoshi Kamiyama, Tohru Saitoh, Takashi Nishikawa, Ryoko Miyanaga
  • Patent number: 5956362
    Abstract: A vertical cavity type semiconductor light emitting device includes: a light emitting layer made of a II-IV group compound semiconductor material; a first II-VI group compound semiconductor layer which has an opening at a position corresponding to the inside of the light emitting layer; and an upper mirror and a lower mirror which are provided so as to interpose the light emitting layer therebetween. A current is injected through the opening into the light emitting layer.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: September 21, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Shigeo Yoshii
  • Patent number: 5822347
    Abstract: In a II-VI group semiconductor laser, on an n type GaAs substrate, an n type ZnSe layer, a multiquantum well layer of a ZnCdSe well layer and a ZnSe barrier layer, and a p type ZnSe layer are deposited in this order. A polycrystalline ZnO layer is provided on both sides of the p type ZnSe layer for constricting current. Multifilm reflecting mirrors, respectively constituted with a polycrystalline SiO.sub.2 layer and a polycrystalline TiO.sub.2 layer, for obtaining laser oscillation are provided on the p type ZnSe layer as well as on a surface of the n type ZnSe layer exposed by etching the GaAs substrate. Furthermore, a p type AuPd electrode and an n type AuGeNi electrode are respectively provided.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: October 13, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Shigeo Yoshii, Yoichi Sasai
  • Patent number: 5488234
    Abstract: Ions are implanted to the n-type or p-type semiconductor layers of a semiconductor element, which includes a semiconductor having a multilayer structure on a substrate, a metal electrode on one entire surface of the semiconductor and a metal section partially formed on the metal electrode, in an amount from 10.sup.12 ions/cm.sup.2 to 10.sup.18 ions/cm.sup.2, thus forming an insulating layer in the n-type or p-type semiconductor layers.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: January 30, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Kazuhiro Okawa, Ayumi Tsujimura, Tsuneo Mitsuyu