Patents by Inventor Shigeru Kanematsu
Shigeru Kanematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11682720Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.Type: GrantFiled: March 20, 2019Date of Patent: June 20, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Satoshi Taniguchi, Masashi Yanagita, Katsuhiko Takeuchi, Shigeru Kanematsu, Takanori Higashi
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Patent number: 11127743Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.Type: GrantFiled: November 4, 2016Date of Patent: September 21, 2021Assignee: SONY CORPORATIONInventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
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Publication number: 20210111277Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.Type: ApplicationFiled: March 20, 2019Publication date: April 15, 2021Inventors: SATOSHI TANIGUCHI, MASASHI YANAGITA, KATSUHIKO TAKEUCHI, SHIGERU KANEMATSU, TAKANORI HIGASHI
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Publication number: 20190035922Abstract: A semiconductor device includes a substrate and a first contact layer on the substrate. The semiconductor device includes a channel layer on the first contact layer and a barrier layer on the channel layer. The semiconductor device includes a gate electrode on at least one side surface of the barrier layer and a second contact layer on the channel layer. The semiconductor device includes a first electrode on the first contact layer and a second electrode on the second contact layer.Type: ApplicationFiled: January 13, 2017Publication date: January 31, 2019Applicant: SONY CORPORATIONInventors: Katsuhiko TAKEUCHI, Shigeru KANEMATSU, Masashi YANAGITA
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Publication number: 20180358359Abstract: [Object] To provide a transistor, a semiconductor device, and an electronic apparatus with reduced parasitic resistance. [Solution] A transistor including: a carrier transit layer including a compound semiconductor; a carrier supply layer provided on and in contact with the carrier transit layer and including a compound semiconductor of a different type from the carrier transit layer; a gate electrode provided on the carrier supply layer; and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.Type: ApplicationFiled: November 4, 2016Publication date: December 13, 2018Inventors: SHIGERU KANEMATSU, KATSUHIKO TAKEUCHI, MASASHI YANAGITA, SHINICHI WADA
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Patent number: 9336895Abstract: A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed.Type: GrantFiled: April 8, 2013Date of Patent: May 10, 2016Assignee: SONY CORPORATIONInventors: Yuki Yanagisawa, Shigeru Kanematsu, Matsuo Iwasaki
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Patent number: 9257574Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.Type: GrantFiled: August 21, 2013Date of Patent: February 9, 2016Assignee: SONY CORPORATIONInventors: Shigeru Kanematsu, Masashi Yanagita
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Publication number: 20150302932Abstract: A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed.Type: ApplicationFiled: April 8, 2013Publication date: October 22, 2015Inventors: Yuki Yanagisawa, Shigeru Kanematsu, Matsuo Iwasaki
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Patent number: 9087888Abstract: A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.Type: GrantFiled: February 25, 2014Date of Patent: July 21, 2015Assignee: Sony CorporationInventors: Masashi Yanagita, Shigeru Kanematsu
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Publication number: 20140252417Abstract: A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.Type: ApplicationFiled: February 25, 2014Publication date: September 11, 2014Applicant: Sony CorporationInventors: Masashi Yanagita, Shigeru Kanematsu
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Patent number: 8797782Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.Type: GrantFiled: February 14, 2012Date of Patent: August 5, 2014Assignee: Sony CorporationInventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
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Publication number: 20140061846Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.Type: ApplicationFiled: August 21, 2013Publication date: March 6, 2014Applicant: Sony CorporationInventors: Shigeru Kanematsu, Masashi Yanagita
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Patent number: 8611129Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.Type: GrantFiled: January 30, 2012Date of Patent: December 17, 2013Assignee: Sony CorporationInventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
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Publication number: 20120212992Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.Type: ApplicationFiled: February 14, 2012Publication date: August 23, 2012Applicant: SONY CORPORATIONInventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
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Publication number: 20120212991Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.Type: ApplicationFiled: January 30, 2012Publication date: August 23, 2012Applicant: SONY CORPORATIONInventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
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Patent number: 7227222Abstract: The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a first conductivity type substrate, first semiconductor layer of a first conducting type with an impurity concentration lower than the substrate and a second semiconductor layer of a second conducting type on the first layer, an insulating film formed on this high-resistance semiconductor layer, and an inductor formed on this insulating film. The inductor has conducting film defining a width of the inductor. The first and second semiconductor layers are each formed under and at least as long as the width of the inductor.Type: GrantFiled: January 16, 2002Date of Patent: June 5, 2007Assignee: Sony CorporationInventor: Shigeru Kanematsu
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Patent number: 7192826Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p?-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.Type: GrantFiled: August 4, 2004Date of Patent: March 20, 2007Assignee: Sony CorporationInventors: Hirokazu Ejiri, Shigeru Kanematsu
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Patent number: 7015551Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: GrantFiled: April 7, 2005Date of Patent: March 21, 2006Assignee: Sony CorporationInventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Patent number: 7009259Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: GrantFiled: April 7, 2005Date of Patent: March 7, 2006Assignee: Sony CorporationInventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Publication number: 20050230762Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: ApplicationFiled: April 7, 2005Publication date: October 20, 2005Inventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu