Patents by Inventor Shigeru Kanematsu
Shigeru Kanematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050230762Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: ApplicationFiled: April 7, 2005Publication date: October 20, 2005Inventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Publication number: 20050202623Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: ApplicationFiled: April 7, 2005Publication date: September 15, 2005Inventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Patent number: 6903424Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: GrantFiled: February 3, 2003Date of Patent: June 7, 2005Assignee: Sony CorporationInventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Publication number: 20050006720Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p?-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.Type: ApplicationFiled: August 4, 2004Publication date: January 13, 2005Inventors: Hirokazu Ejiri, Shigeru Kanematsu
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Patent number: 6791160Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.Type: GrantFiled: February 14, 2002Date of Patent: September 14, 2004Assignee: Sony CorporationInventors: Hirokazu Ejiri, Shigeru Kanematsu
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Publication number: 20040115893Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) which are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities such as phosphorous in the semiconductor substrate (1). This invention greatly contributes curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics such as a current amplification factor and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.Type: ApplicationFiled: October 6, 2003Publication date: June 17, 2004Inventors: Kenichi Ookubo, Hideki Mori, Shigeru Kanematsu
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Publication number: 20030151115Abstract: The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a substrate, a semiconductor layer (high-resistance semiconductor layer) formed on this substrate that has an impurity concentration lower than the impurity concentration of the substrate or a first semiconductor layer (high-resistance semiconductor layer) of a first conducting type with an impurity concentration lower than the substrate and a second semiconductor layer of a second conducting type on the first layer, an insulating film formed on this high-resistance semiconductor layer (semiconductor layer, first semiconductor layer), and an inductor formed on this insulating film.Type: ApplicationFiled: April 8, 2003Publication date: August 14, 2003Inventor: Shigeru Kanematsu
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Patent number: 6548873Abstract: A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.Type: GrantFiled: October 12, 1999Date of Patent: April 15, 2003Assignee: Sony CorporationInventors: Hiroaki Ammo, Hiroyuki Miwa, Shigeru Kanematsu
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Publication number: 20020123178Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.Type: ApplicationFiled: February 14, 2002Publication date: September 5, 2002Inventors: Hirokazu Ejiri, Shigeru Kanematsu
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Publication number: 20020033509Abstract: There is provided a semiconductor device which causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire comprising a barrier metal made of a titanium material is provided. The semiconductor device comprises a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film-and a second silicon oxide film-provided on the semiconductor substrate while covering the MOS transistor and a wire having a barrier metal made of a titanium material and provided on the insulating film, and is characterized in that the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film may be what is formed in one and same process with that of a dielectric film of a capacitor element.Type: ApplicationFiled: October 12, 1999Publication date: March 21, 2002Inventors: HIROAKI AMMO, HIROYUKI MIWA, SHIGERU KANEMATSU
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Patent number: 5856228Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.Type: GrantFiled: November 27, 1996Date of Patent: January 5, 1999Assignee: Sony CorporationInventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
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Patent number: 5830799Abstract: To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference.Type: GrantFiled: August 20, 1996Date of Patent: November 3, 1998Assignee: Sony CorporationInventors: Hiroaki Ammo, Shigeru Kanematsu, Takayuki Gomi
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Patent number: 5643806Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.Type: GrantFiled: June 7, 1995Date of Patent: July 1, 1997Assignee: Sony CorporationInventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
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Patent number: 5541124Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.Type: GrantFiled: June 7, 1995Date of Patent: July 30, 1996Assignee: Sony CorporationInventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi