Patents by Inventor Shigeru Mori

Shigeru Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190115283
    Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 18, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Maki HASEGAWA, Shuhei YOKOYAMA, Shigeru MORI, Hisashi KAWAFUJI
  • Publication number: 20190103297
    Abstract: It is an object to provide a technique capable of providing a semiconductor device with information indicating a plurality of electrical characteristics. A semiconductor device sorting system includes a characteristic measurement unit measuring electrical characteristics of a semiconductor device, a rank determination database for classifying the electrical characteristics into ranks, a calculation unit classifying the plurality of electrical characteristics of the semiconductor device measured by the characteristic measurement unit into a plurality of ranks with reference to the rank determination database, a writing unit converting the plurality of ranks classified by the calculation unit into a graphic symbolic code and forming the graphic symbolic code on the semiconductor device, a reading unit reading the plurality of ranks from the graphic symbolic code formed on the semiconductor device, and a sorting unit sorting the semiconductor device based on the plurality of ranks being read by the reading unit.
    Type: Application
    Filed: August 27, 2018
    Publication date: April 4, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shuhei YOKOYAMA, Maki HASEGAWA, Hiroyuki NAKAMURA, Shigeru MORI, Toru IWAGAMI
  • Publication number: 20180226630
    Abstract: {Problem} Provided is a roll-press machine provided with a wrinkle occurrence prevention device for suppressing occurrence of wrinkles caused by a roll-pressing operation on a coated part and an uncoated part of an electrode plate, and a roll-pressing method. {Solution} A work roll having a diameter smaller than that of the pressing roll is pressed to allow the uncoated part to be rolled between the pressing roll and the work roll, and the work roll is held by two backup rolls arranged in a V-shape formation so that the work roll can press the uncoated part with a pressing force uniform in width-wise.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 9, 2018
    Inventors: Katsuhiko YANAI, Shigeru MORI
  • Publication number: 20170232491
    Abstract: [Problem] In a small-size rolling mill or a roll press machine, to provide a hydraulic screw-down device compatible with the plate thickness accuracy without using a hydraulic control servo valve. [Means for Solution]A hydraulic screw-down device that is comprised of a screw to move a piston arranged in a booster cylinder back and forth, and a motor that gives rotational force to the screw controlling freely the rotational angle of the screw so as to move the piston to the purpose position. A screw-down cylinder connected with the booster cylinder through piping makes a ram in the screw-down cylinder move vertically by the move of oil caused by the movement of the piston in the booster cylinder and thereby enables push-up and push-down of the mill roll.
    Type: Application
    Filed: October 27, 2016
    Publication date: August 17, 2017
    Inventors: Katsuhiko YANAI, Shigeru MORI
  • Patent number: 9550360
    Abstract: Provided are a manufacturing method of an inkjet print head, the inkjet print head and a drawing apparatus equipped with the inkjet print head. The manufacturing method includes: forming a separation assisting layer on a substrate; forming heating resistors, thin-film transistors and nozzles for ejecting liquid, on the separation assisting layer; separating the separation assisting layer from the substrate; forming a first heat-conductive layer on the opposite surface of the separation assisting layer from the nozzles; and forming an ink supply port for supplying ink to the nozzles from a first heat-conductive layer side of the inkjet print head.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 24, 2017
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Shigeru Mori, Setsuo Kaneko, Hideki Asada
  • Publication number: 20160046127
    Abstract: Provided are a manufacturing method of an inkjet print head, the inkjet print head and a drawing apparatus equipped with the inkjet print head. The manufacturing method includes: forming a separation assisting layer on a substrate; forming heating resistors, thin-film transistors and nozzles for ejecting liquid, on the separation assisting layer; separating the separation assisting layer from the substrate; forming a first heat-conductive layer on the opposite surface of the separation assisting layer from the nozzles; and forming an ink supply port for supplying ink to the nozzles from a first heat-conductive layer side of the inkjet print head.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 18, 2016
    Inventors: Shigeru MORI, Setsuo KANEKO, Hideki ASADA
  • Patent number: 9211708
    Abstract: Provided are a manufacturing method of an inkjet print head, the inkjet print head and a drawing apparatus equipped with the inkjet print head. The manufacturing method includes: forming a separation assisting layer on a substrate; forming heating resistors, thin-film transistors and nozzles for ejecting liquid, on the separation assisting layer; separating the separation assisting layer from the substrate; forming a first heat-conductive layer on the opposite surface of the separation assisting layer from the nozzles; and forming an ink supply port for supplying ink to the nozzles from a first heat-conductive layer side of the inkjet print head.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 15, 2015
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Shigeru Mori, Setsuo Kaneko, Hideki Asada
  • Publication number: 20150042725
    Abstract: Provided are a manufacturing method of an inkjet print head, the inkjet print head and a drawing apparatus equipped with the inkjet print head. The manufacturing method includes: forming a separation assisting layer on a substrate; forming heating resistors, thin-film transistors and nozzles for ejecting liquid, on the separation assisting layer; separating the separation assisting layer from the substrate; forming a first heat-conductive layer on the opposite surface of the separation assisting layer from the nozzles; and forming an ink supply port for supplying ink to the nozzles from a first heat-conductive layer side of the inkjet print head.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Inventors: SHIGERU MORI, SETSUO KANEKO, HIDEKI ASADA
  • Patent number: 8912583
    Abstract: The present invention provides a thin-film transistor manufactured on a transparent substrate having a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate; wherein the channel region having channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film; the light blocking film is divided across the channel region; and interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d). Thereby, the cost for manufacturing the thin-film transistor is low, and the photo leak current of the thin-film transistor is suppressed.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 16, 2014
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Takahiro Korenari, Hiroshi Tanabe
  • Patent number: 8779512
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 15, 2014
    Assignees: NEC Corporation, NLT Technologies, Ltd.
    Inventor: Shigeru Mori
  • Patent number: 8570455
    Abstract: A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 29, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Isao Shouji, Hiroshi Tanabe
  • Patent number: 8431447
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 30, 2013
    Assignees: NEC Corporation, NLT Technologies, Ltd.
    Inventor: Shigeru Mori
  • Patent number: 8334553
    Abstract: A thin-film transistor manufactured on a transparent substrate has a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate. The channel region has channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film. The light blocking film is divided across the channel region. Interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d), allowing low the manufacturing cost and suppressed photo leak current.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 18, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Takahiro Korenari, Hiroshi Tanabe
  • Patent number: 8330193
    Abstract: The present invention provides a high-performance silicon oxide film as a gate insulation film and a semiconductor device having superior electric characteristics. The silicon oxide film according to the present invention includes CO2 in the film, wherein, when an integrated intensity of a peak is expressed by (peak width at half height)×(peak height) in an infrared absorption spectrum, the integrated intensity of a CO2-attributed peak which appears in the vicinity of a wave number of 2,340 cm?1 is 8E-4 times or more with respect to the integrated intensity of an SiO2-attributed peak which appears in the vicinity of a wave number of 1,060 cm?1.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 11, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Hiroshi Tanabe, Jun Tanaka
  • Publication number: 20120058646
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 8, 2012
    Applicants: NEC LCD TECHNOLOGIES, LTD., NEC CORPORATION
    Inventor: SHIGERU MORI
  • Patent number: 8080850
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: December 20, 2011
    Assignees: NEC Corporation, NEC LCD Technologies, Ltd.
    Inventor: Shigeru Mori
  • Publication number: 20110198607
    Abstract: A thin-film transistor manufactured on a transparent substrate has a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate. The channel region has channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film. The light blocking film is divided across the channel region. Interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d), allowing low the manufacturing cost and suppressed photo leak current.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 18, 2011
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shigeru MORI, Takahiro KORENARI, Hiroshi TANABE
  • Patent number: 7981811
    Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: July 19, 2011
    Assignees: NEC Corporation, NEC LCD Technologies, Ltd
    Inventors: Shigeru Mori, Takahiro Korenari, Tadahiro Matsuzaki, Hiroshi Tanabe
  • Publication number: 20110013107
    Abstract: A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.
    Type: Application
    Filed: March 30, 2009
    Publication date: January 20, 2011
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shigeru Mori, Isao Shouji, Hiroshi Tanabe
  • Publication number: 20100283106
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: November 11, 2010
    Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTD.
    Inventor: Shigeru MORI