Abstract: An information processing apparatus using proximity wireless communication is provided. The information processing apparatus includes a detection unit that includes a plurality of capacitance sensors arranged in a two-dimensional array along an operation surface and a recognition unit that recognizes an object placed on the operation surface on the basis of a detection result of the detection unit. The recognition unit recognizes a position and a direction of the capacitance sensor on which the metal portion included in the object is placed on the basis of the detection result obtained by discarding a detection value less than a predetermined threshold and recognizes a position and a direction less than an interval between the capacitance sensors in the metal portion on the basis of the detection result in which the detection value less than the predetermined threshold is not discarded.

Abstract: An information processing apparatus using proximity wireless communication is provided. The information processing apparatus includes a detection unit that includes a plurality of capacitance sensors arranged in a two-dimensional array along an operation surface and a recognition unit that recognizes an object placed on the operation surface on the basis of a detection result of the detection unit. The recognition unit recognizes a position and a direction of the capacitance sensor on which the metal portion included in the object is placed on the basis of the detection result obtained by discarding a detection value less than a predetermined threshold and recognizes a position and a direction less than an interval between the capacitance sensors in the metal portion on the basis of the detection result in which the detection value less than the predetermined threshold is not discarded.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: A mask capable of improving accuracy of transferring a pattern by making the configuration of a beam portion regular and simple, an exposure method using the mask and a production method of a semiconductor device; wherein the beam portion is composed of a first beam portion wherein a plurality of first beams extending by inclining with respect to the X axis and Y axis are arranged at regular intervals and a second beam portion wherein a plurality of second beams extending by inclining with respect to the X axis and Y axis and intersecting with the first beams are arranged at regular intervals, and the beam configuration is made regular on all region surrounded by a supporting frame; four unit exposure regions for performing exposure by being superimposed on an object to be exposed are set in the region surrounded by the supporting frame, and a membrane of at least two unit exposure regions exists at any position when superimposing the four unit exposure regions.

Abstract: To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data ?1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data ?1 (ST13).

Abstract: An exposure method and a semiconductor device production method that control a rise in temperature of a mask irradiated by a charged particle beam. A displacement of the position of a pattern accompanying with the rise in temperature of the mask and the pattern are projected on an exposed object with a high accuracy. After an electron beam scans one scan line, scan lines are jumped by over a number of scan lines and the electron beam scans the next scan line. Since the number of the overjumped lines is a set number that control the temperature rise of a membrane by overlapping of the electron beam, the temperature rise is controlled by an interlaced-scanning. After one interlaced-scanning, similar to the above the scan lines are jumped over by the predetermined number of scan lines and the electron beam scans the next scan lines.

Abstract: A data storage device includes a memory, a record controller, and a management area setting unit. The method has first and second management areas for recording address information indicative of valid data areas, and a security area for recording information corresponding to address information recorded in either one of the first and second management areas. The record controller rewrites information recorded in the security area after the address information recorded in either one of the first and second management areas has been updated, into information corresponding to the updated address information. The management area setting unit sets either one of the first and second management areas as a valid management area based on the information recorded in the security area.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data ?1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data ?1 (ST13).

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.