Abstract: A mask capable of improving accuracy of transferring a pattern by making the configuration of a beam portion regular and simple, an exposure method using the mask and a production method of a semiconductor device; wherein the beam portion is composed of a first beam portion wherein a plurality of first beams extending by inclining with respect to the X axis and Y axis are arranged at regular intervals and a second beam portion wherein a plurality of second beams extending by inclining with respect to the X axis and Y axis and intersecting with the first beams are arranged at regular intervals, and the beam configuration is made regular on all region surrounded by a supporting frame; four unit exposure regions for performing exposure by being superimposed on an object to be exposed are set in the region surrounded by the supporting frame, and a membrane of at least two unit exposure regions exists at any position when superimposing the four unit exposure regions.

Abstract: A mask for fabrication of semiconductor devices in which the membrane layer keeps high strength and is free of stress and distortion even though it is made thin. The mask has a membrane-supporting layer at the peripheral part of the mask pattern or the mask pattern region in the membrane layer constituting the mask.

Abstract: A mask capable of improving superimposing accuracy of patterns drawn on a plurality of masks, a production method of a semiconductor device capable of improving a yield of semiconductor devices, and a semiconductor device wherein a pattern can be made finer are provided.

Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

Abstract: To provide an exposure apparatus, the exposure method and a semiconductor device production method that rise in temperature of a mask by irradiating a charged particle beam can be controlled, displacement of the position of a pattern accompanying with rise in temperature of the mask and the pattern can be projected on an exposed object with a high accuracy. After an electron beam scans on one scan line, scan lines are jumped over number of scan lines and the electron beam scans on the next scan line. Since number of said overjumped lines is set number that can be control rise in temperature of a membrane by overlapping of the electron beam, rise in temperature is controlled by the interlaced-scanning. After once interlaced-scanning, for the scan line, as similar to the above the scan lines are jumped over predetermined number of scan lines and the electron beam scans on the scan lines. By repeating the above interlaced-scan, the set electron beam scans on all the scan lines.

Abstract: A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided.

Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: A method of lithography capable of optimizing its process condition more simply and precisely based on a limited number of experiments is provided. A line edge roughness of a resist pattern is obtained as a characteristic value for evaluation. The resist pattern is formed in an orthogonal experiment based on an orthogonal table that includes significant factors, which define a process condition of its lithography. Reference level (benchmark) values are set for each factor in the orthogonal experiment, from which an appropriate reference level value which minimizes the edge roughness is selected as a process condition for proceeding with the lithography.

Abstract: A mask for fabrication of semiconductor devices in which the membrane layer keeps high strength and is free of stress and distortion even though it is made thin. The mask has a membrane-supporting layer at the peripheral part of the mask pattern or the mask pattern region in the membrane layer constituting the mask.

Abstract: The present invention relates to a method of computing a defocus amount in lithography and lithographic process using the method. A first step executes plural double-exposure operations each including a pattern exposure for forming a pattern of a predetermined line width and a full-area exposure over an area covering the pattern, employing different dosages employed in the full-area exposures for different double-exposure operations. A developing operation is performed. subsequent to the double-exposure, whereby a plurality of resist patterns are obtained. In a second step, the edge roughness and the line width are measured on each resist pattern. In a third step, a Gaussian function is fitted to the edge roughnesses and the line widths. The distribution width of the Gaussian curve is determined as the defocus amount of a pseudo-profile of the beam which indicates a change in lithographic factors that affect the accuracy of lithography.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: In an image processor, a decider decides based on image data of pixels included in a block whether the block has character attribute of non-character attribute, a first encoder encodes the image data with block truncation coding, and a second encoder encodes the image data which have been encoded by the first encoder. For a block of character attribute, the binarized data binarized by the binarizer are encoded by the first and second encoders. For a block of non-character attribute, the image data are encoded by the first and second encoders without binarization. In a different image processor, it is decide whether image data of pixels in an area consisting of a plurality of blocks are all character, all ground or mixture of character and ground. Then, an encoder encodes the image data in each block differently according to the decision.

Abstract: A method of lithography capable of optimizing its process condition more simply and precisely based on a limited number of experiments is provided. A line edge roughness of a resist pattern is obtained as a characteristic value for evaluation. The resist pattern is formed in an orthogonal experiment based on an orthogonal table that includes significant factors, which define a process condition of its lithography. Reference level (benchmark) values are set for each factor in the orthogonal experiment, from which an appropriate reference level value which minimizes the edge roughness is selected as a process condition for proceeding the lithography.

Abstract: In an image processor, image data of red, green and blue are converted to image data of lightness and chromaticities, and they are divided into pixel blocks. Then, image data of each block are compressed to data having 4 gradation levels smaller than 256 levels of the image data by generalized block truncation coding. Then a capacity of image memory can be decreased. An attribute of the image data is decided for each block according to the compressed data. The attribute can be corrected by taking attributes of adjacent blocks into account. Edition of image data such as edge emphasis can be performed according to the attributes. The compressed data are further compressed by deleting data which can be specified according to the attribute.