Patents by Inventor Shigeru Shiratake
Shigeru Shiratake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669172Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: June 4, 2012Date of Patent: March 11, 2014Assignee: Renesas Electronics CorporationInventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Publication number: 20120238089Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: Renesas Electronics CorporationInventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Patent number: 8211777Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: March 19, 2010Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Patent number: 8129770Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.Type: GrantFiled: January 13, 2010Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventor: Shigeru Shiratake
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Patent number: 8105907Abstract: To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.Type: GrantFiled: January 29, 2010Date of Patent: January 31, 2012Assignee: Elpida Memory, Inc.Inventors: Eiji Hasunuma, Shigeru Shiratake, Takeshi Ohgami
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Patent number: 7935595Abstract: A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).Type: GrantFiled: October 17, 2006Date of Patent: May 3, 2011Assignee: Elpida Memory Inc.Inventor: Shigeru Shiratake
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Publication number: 20110034005Abstract: A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).Type: ApplicationFiled: October 15, 2010Publication date: February 10, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Shigeru SHIRATAKE
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Publication number: 20100197097Abstract: To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.Type: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Eiji HASUNUMA, Shigeru SHIRATAKE, Takeshi OHGAMI
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Publication number: 20100190330Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: March 19, 2010Publication date: July 29, 2010Applicant: Renesas Technology Corp.Inventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Publication number: 20100109064Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.Type: ApplicationFiled: January 13, 2010Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventor: Shigeru SHIRATAKE
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Patent number: 7709324Abstract: Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101s, a protective film 102, and the silicon nitride film 103. A gate insulating film 109 is then formed on the inner walls of the gate trenches 108, and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108. The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.Type: GrantFiled: October 10, 2006Date of Patent: May 4, 2010Assignee: Elpida Memory, Inc.Inventor: Shigeru Shiratake
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Patent number: 7705392Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: April 13, 2006Date of Patent: April 27, 2010Assignee: Renesas Technology Corp.Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Patent number: 7674673Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.Type: GrantFiled: January 24, 2008Date of Patent: March 9, 2010Assignee: Renesas Technology Corp.Inventor: Shigeru Shiratake
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Publication number: 20100044772Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuaki YONEMOCHI, Hisakazu OTOI, Akio NISHIDA, Shigeru SHIRATAKE
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Publication number: 20080124862Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.Type: ApplicationFiled: January 24, 2008Publication date: May 29, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventor: Shigeru SHIRATAKE
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Patent number: 7339221Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.Type: GrantFiled: October 12, 2004Date of Patent: March 4, 2008Assignee: Renesas Technology Corp.Inventor: Shigeru Shiratake
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Publication number: 20080017904Abstract: A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.Type: ApplicationFiled: July 6, 2007Publication date: January 24, 2008Inventors: Satoru AKIYAMA, Ryuta Tsuchiya, Tomonori Sekiguchi, Riichiro Takemura, Masayuki Nakamura, Yasushi Yamazaki, Shigeru Shiratake
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Publication number: 20070096204Abstract: A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).Type: ApplicationFiled: October 17, 2006Publication date: May 3, 2007Inventor: Shigeru Shiratake
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Publication number: 20070082440Abstract: Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101s, a protective film 102, and the silicon nitride film 103. A gate insulating film 109 is then formed on the inner walls of the gate trenches 108, and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108. The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.Type: ApplicationFiled: October 10, 2006Publication date: April 12, 2007Inventor: Shigeru Shiratake
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Publication number: 20060231884Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: April 13, 2006Publication date: October 19, 2006Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake