Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

Abstract: A semiconductor device having a memory cell portion and a peripheral circuit portion is provided which achieves suppression of reduction of punch-through margin of transistors in the peripheral circuit portion and offers ensured short margin and enhanced current driving capability. After a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to improve burying characteristics after formation of an interlayer insulating film, and also after a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to enhance refresh characteristics after formation of contact plugs in the memory cell portion, a silicon oxide film and insulating film formed on a semiconductor substrate in the peripheral circuit portion are removed by anisotropic dry-etching, leaving the insulating film as sidewall insulating films on sides of sidewall nitride films.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: A semiconductor device having a memory cell portion and a peripheral circuit portion is provided which achieves suppression of reduction of punch-through margin of transistors in the peripheral circuit portion and offers ensured short margin and enhanced current driving capability. After a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to improve burying characteristics after formation of an interlayer insulating film, and also after a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to enhance refresh characteristics after formation of contact plugs in the memory cell portion, a silicon oxide film and insulating film formed on a semiconductor substrate in the peripheral circuit portion are removed by anisotropic dry-etching, leaving the insulating film as sidewall insulating films on sides of sidewall nitride films.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.

Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

Abstract: A semiconductor device with a fuse box includes at least two gate electrodes 8, 9 and a fuse member 6. The two gate electrodes 8, 9 are formed on at least one insulating film 13 on a semiconductor substrate 100. The fuse member 6 is formed on the insulating film 13 on the semiconductor substrate 100. The two gate electrodes 8, 9 are electrically connected each other by the fuse member 6. In addition, the insulating film 13 and a field region 2 constituted by a semiconductor region are arranged adjacent to each other in a frame-like guard ring 1. The guard ring 1 is constituted by a semiconductor region formed on the semiconductor substrate 100.

Abstract: A silicon nitride film is formed above a semiconductor substrate so as to cover a gate electrode. Next, a silicon thermal oxidation film is formed on the surface of the silicon nitride film by carrying out thermal oxidation processing on the silicon nitride film. In the case that a pinhole exists in the silicon nitride film, the inside of the pinhole is also oxidized so as to be filled in with the silicon thermal oxidation film. Next, a silicon nitride film is formed by carrying out anisotropic etching on the silicon nitride film. After that, a contact hole is formed in the silicon oxide film, which is formed above the semiconductor substrate. A bit line contact part is formed within the contact hole and, then, a bit line is formed. Thereby, a semiconductor device is gained wherein an electrical short circuit can be prevented.

Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

Abstract: A semiconductor device with a fuse box includes at least two gate electrodes 8, 9 and a fuse member 6. The two gate electrodes 8, 9 are formed on at least one insulating film 13 on a semiconductor substrate 100. The fuse member 6 is formed on the insulating film 13 on the semiconductor substrate 100. The two gate electrodes 8, 9 are electrically connected each other by the fuse member 6. In addition, the insulating film 13 and a field region 2 constituted by a semiconductor region are arranged adjacent to each other in a frame-like guard ring 1. The guard ring 1 is constituted by a semiconductor region formed on the semiconductor substrate 100.

Abstract: A semiconductor device has a plurality of fuse members (1a, 1b) composed of a metal that can be cut by laser light (4), disposed over a semiconductor substrate (5). The length L of the fuse members (1a, 1b) is smaller than a value obtained by subtracting an alignment error .alpha. of the laser light (4) from a spot diameter D of the laser light (4), i.e., the value (D-.alpha.). The fuse members (1a, 1b) are spaced a distance l larger than a value obtained by adding the alignment error .alpha. to the half of the spot diameter D, i.e., the value (D/2+.alpha.).

Abstract: There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode.

Abstract: There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode.

Abstract: In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern.

Abstract: An isolating/insulating film is formed on the surface of a p.sup.- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating oxide film. A p.sup.+ impurity diffusion region is formed on the p.sup.- silicon substrate in such a manner as to be contacted with the lower surface of the isolating oxide film in the element isolating region and to extend at a specified depth from the surface of the p.sup.- silicon substrate in the element forming region. A p-type impurity diffusion region having a p-type impurity concentration higher than that of the p.sup.- silicon substrate is formed at the side end portion of the isolating oxide film in such a manner as to be contacted with the n-type source/drain region. With this arrangement, it is possible to reduce leakage current caused by the distribution of crystal defects in a depletion layer.