Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

Abstract: With a semiconductor device and according to a manufacturing method of the invention, a trade-off relationship between a threshold value and a diffusion layer leak is eliminated, and it is not necessary to form a gate oxide film at a plurality of steps. Gate electrodes (4A, 4B and 4C) respectively comprise a polysilicon layer (M1) and a WSi layer (L1), the polysilicon layer (M1) and a WSi layer (L2), the polysilicon layer (M1) and a WSi layer (L3), which are respectively stacked in this order on a gate oxide film (3). Channel dope layers (103A, 103B and 103C) are formed within a well layer (101) respectively under the gate electrodes (4A, 4B and 4C).

Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.

Abstract: In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.

Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

Abstract: The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.

Abstract: A thin film transistor includes an active layer having an offset region formed between a channel region and a drain region, a first insulating film formed on an upper surface of the active layer, a gate electrode formed at a position opposing to the channel region with the first insulating film interposed, and a second insulating film formed at a position opposing to the offset region with the first insulating film interposed and including impurities for forming charges. The charges formed in the second insulating film are provided by implanting fluorine ions, for example, if the charges are to be negative charges. By this structure, the on current of the thin film transistor can be increased and the leak current can be reduced.

Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

Abstract: An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

Abstract: A semiconductor device having at least one transistor having a channel member spaced from a semiconductor substrate, an insulating film on the substrate, and a control electrode on the channel member covering the channel member. The control electrode forms a channel in each of two opposed surfaces of the channel member. The channel member is a polycrystalline semiconductor.

Abstract: A method of manufacturing a semiconductor device including forming an insulating film on a substrate; forming an opening in the insulating film by anisotropic etching; embedding a dummy member in the opening; forming a channel member over the insulating film and the dummy member; removing the dummy member to form a gap in the opening between the channel member and the substrate; and forming a thin film on the channel member and in the gap covering the channel member, the thin film being a control electrode of a transistor for forming channels on opposite sides of the channel member.

Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A second silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6). In addition, the thin-film transistor includes a semiconductor layer covering a gate electrode. The semiconductor layer includes source, drain and active regions. The active region preferably includes a smaller amount of fluorine than the gate electrode.

Abstract: A solid-state imaging device includes a semiconductor substrate in which an element part including a plurality of light responsive elements for generating charge carriers in response to incident light and a transfer part for transferring the charge carriers generated in each light responsive element are incorporated; a lens layer is disposed on the element part so that incident light is collected in the light responsive elements; and a light beam dispersion layer is disposed between the lens layer and the element part and includes two light transmissive layers having different refractive indices for dispersing light collected by the lens layer so that collected light entering respective light responsive elements is closer to a parallel beam than the incident light. By suppressing broadening of incident light in the semiconductor substrate at the light responsive elements, fewer charge carriers enter the CCD channel region and smear is reduced.

Abstract: A method for producing a solid-state imaging device including a photodetector including implanting two different dopant impurity ions, each producing the second conductivity type and having different diffusion coefficients in a first conductivity type semiconductor layer; thermally diffusing the implanted ions to produce a second conductivity type region including a relatively deep second conductivity type subregion and a relatively shallow second conductivity type region having a higher dopant impurity concentration than said relatively deep second conductivity type subregion; forming a charge transfer electrode on said semiconductor layer such that an edge of said electrode lies adjacent part of the junction between said semiconductor layer and said second conductivity type region; and implanting a dopant impurity producing the first conductivity type in said second relatively shallow second conductivity type subregion using said charge transfer electrode as a mask to produce a first conductivity type impur

Abstract: A solid-state imaging device includes a photodetector having a first conductivity type semiconductor layer, a second conductivity type semiconductor region in the layer, and a first conductivity type region in the second conductivity type region. The second conductivity type semiconductor region includes second conductivity type subregions having different dopant impurity concentrations. The subregion which contacts the first conductivity type region has a dopant impurity concentration higher than the second conductivity type subregion. The device reads out photogenerated charges stored in the second conductivity type region as a light signal. The junction capacitances between the second conductivity type semiconductor region and the first conductivity type layer and the first conductivity type region are increased so that the maximum quantity of stored charge when the first conductivity type region is depleted is increased without a change in the potential.

Abstract: A charge transfer device includes a plurality of spaced apart charge transfer electrodes disposed on a semiconductor substrate with an insulating film intervening between the electrodes and between the substrate and the electrodes. The insulating film between the charge transfer electrodes has a higher dielectric constant than other parts of the insulating layer electrode. The insulating film may also have a higher dielectric constant in the region between part of the charge transfer electrodes and the substrate. Therefore, the flattening of a transfer electrode is achieved in a one-layer electrode structure. In addition, a potential "hollow" produced between adjacent charge transfer electrodes is reduced and the loss of transferred charges is reduced.