Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.

Abstract: According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.

Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.

Abstract: First and second anti-fuse elements are provided for storing 1-bit data. A program voltage generating circuit generates a programming voltage and applies it to the first and second anti-fuse elements. A read voltage generating circuit generates a readout voltage and applies it to the first and second anti-fuse elements. First and second transistors are inserted between the first and second anti-fuse elements and a ground potential node, and are respectively turned on by first and second select signals during the programming period. A switch element is connected between the first and the second transistors. The switch element is turned off during the programming period, and turned on during the readout period. A sense amplifier is connected to the switch element in order to sense the data read out from the first and the second anti-fuse elements.

Abstract: First and second anti-fuse elements are provided for storing 1-bit data. A program voltage generating circuit generates a programming voltage and applies it to the first and second anti-fuse elements. A read voltage generating circuit generates a readout voltage and applies it to the first and second anti-fuse elements. First and second transistors are inserted between the first and second anti-fuse elements and a ground potential node, and are respectively turned on by first and second select signals during the programming period. A switch element is connected between the first and the second transistors. The switch element is turned off during the programming period, and turned on during the readout period. A sense amplifier is connected to the switch element in order to sense the data read out from the first and the second anti-fuse elements.

Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.

Abstract: A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

Abstract: A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

Abstract: A tristate buffers includes a logic circuit which outputs a high-level signal. The output signal is fed to gates of 1st and 2nd P-channel MOS transistors (TRs). A 3rd PMOS TR has a gate connected to a drain of the 2nd PMOS TR, and a drain connected to a drain of the 1st PMOS TR. A 4th PMOS TR has a gate connected to the drain of the 1st PMOS TR, and a drain connected to the drain of the 2nd PMOS TR. A 1st NMOS TR and a 2nd NMOS TR have their drains connected respectively to the drains of the 1st and the 3rd PMOS TRs and the drains of the 2nd and the 4th PMOS TRs. A 3rd NMOS TR and a 4th NMOS TR are connected respectively between the source of the 1st NMOS TR and ground and the source of the 2nd NMOS TR and the ground. The drains of the 1st and the 3rd PMOS TRs and the 1st NMOS TR are connected to an inverter. A 5th PMOS TR is connected to the drains of the 2nd and the 4th PMOS TRs and the 2nd NMOS TR.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed. A semiconductor integrated circuit according to the present invention includes three pieces of first logic operation circuits 1a, 1b and 1c, keeper circuits 2a, 2b and 2c each of which holds output logics of the first logic operation circuits 1a, 1b and 1c, and three inverters IVa, IVb and IVc connected to output terminals of the first logic operation circuits 1a, 1b and 1c, respectively. When an output of any one first logic operation circuit turns to a low level, outputs of the other first logic operation circuits are forcibly set to a high level, and any one output terminal can be hence solely set on the high level.

Abstract: A CAM Cell circuit having a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line is disclosed. The CAM Cell circuit has an exclusive-OR circuit connecting in parallel a circuit having first and second transistors in series-connection. It also has a circuit having third and fourth transistors in series-connection.

Abstract: Object of the present invention is to provide an address converting circuit capable of converting a virtual address that access is required into a physical address. The address converting circuit of the present invention has a CLA circuit, an adder, a CAM, a carryout selector, a physical address storing section, and a physical address selector. When adding both of the upper bit strings of the base address and the offset address that access is required, before the carryout signal from the lower bit string is calculated, addition of both of the upper bit strings in case of presuming the carryout signal as “0” and addition of both of the upper bit strings in case of presuming the carryout signal as “1” are performed. Either of the added results is selected by the carryout signal in order to perform the comparing process. Because of this, it is possible to convert into the physical address at high speed.

Abstract: A decision circuit comprises an exclusive-OR circuit connecting in parallel a circuit having a first, and second transistors in series-connection, and a circuit having a third, and fourth transistors in series-connection; and a pre-charging circuit connecting in series fifth and sixth transistors with different polarity from that of said first to fourth transistors. By reducing the number of the circuit elements and the circuit area, it may be possible to speed up the operation.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: A logic circuit determines the logic based only on a change in electric current. The logic circuit comprises a logical value determination circuit, a reference current generator, and a current sense amplifier. The logical value determination circuit defines a logical current flowing in response to multiple logic-signals. The reference current generator produces a reference current which is used to determine whether the logical current defined by the logical value determination circuit is true or false. The current sense amplifier detects and amplifies a difference between the logic current and the reference current.