Abstract: A high speed impedance matching circuit suitable for use in high speed semiconductor integrated circuits matches the output impedance of a semiconductor device to the impedance of other devices such a computer system bus thereby reducing signal reflections caused by impedance mismatches and which can adversely affect the operation of a high speed computer system. The impedance of an output buffer is matched to the impedance of an external resistor.

Abstract: A latch-type sense amplifier receives a low level differential small swing input signal pair. The amplifier includes a pair of MOSFET switches of a first conductivity type each having a first source/drain terminal coupled to one of the input signal lines. The latch has a second pair of MOSFETs of the first conductivity type with its first source/drain terminal connected to the second source/drain terminal of one of the first pair of MOSFETs. Each of the second pair of MOSFETs has its first source/drain terminal connected to the first source/drain terminal of a third pair of MOSFETs of the second conductivity type. Each MOSFET of the second conductivity type has its second source/drain terminal connected to a first voltage source. The gate terminals of the second pair of MOSFETs are connected together to receive a control signal. The gate terminals of each of the third pair of MOSFETs are cross-coupled and connected to the second source/drain terminals of the first pair of MOSFETs.

Abstract: A cache memory automatically sets a low-, semi-, or high-speed mode operation according to a result of comparison between a half-period of a reference clock signal and a pulse width of a reference pulse signal provided by a reference pulse signal generator. Namely, a start signal generator generates a start signal used to access data memories, according to the frequency of the reference clock signal and a difference between the reference clock and pulse signals. According to the start signal and information indicating a hit tag memory, the cache memory dynamically switches the modes from one to another, without external instructions to the cache memory.

Abstract: A liquid crystal display device of low power consumption is disclosed, which is suitable for use with a portable data processing apparatus, in particular.

Abstract: A semiconductor memory device comprises: a memory cell array having memory cells (1) arranged into a matrix pattern; a plurality of word lines (WL) each for selecting the memory cells arranged in the same line of the memory cell array; a plurality of bit lines (BL, NBL) each connected in common to the memory cells arranged in the same column of the memory cell array, for transmitting and receiving data to and from one of the memory cells selected by one of the word lines; a plurality of first column decoders (FCD) each for selectively connecting one of a predetermined number of the bit lines to one of a plurality of first common data lines (FDL, FNDL); a plurality of writing transistors (2) each provided for one of a plurality of the first common data lines and each having a data input line for inputting data applied from the outside thereto, the data inputted from the outside through the data input line being written in one of the selected memory cells so that data of a plurality of bits can be simultaneousl

Abstract: The external power supply voltage applied to an external power supply terminal is supplied to an internal stepdown circuit and a switch circuit. The value of the external power supply voltage is detected by an external voltage detecting circuit, and if the value is greater than a predetermined value, the internal stepdown circuit operates, the external power supply voltage is stepped down by the internal stepdown circuit and supplied to an internal circuit as an internal power supply voltage. Alternatively, if the value of the external power supply voltage is smaller than the predetermined value, the internal stepdown circuit does not operate, and instead the switch circuit operates and the external power supply voltage is supplied via the switch circuit to the internal circuit as the internal power supply voltage.

Abstract: An internal row address signal output from an address buffer is supplied to first and second row partial decoders. A programming circuit is programmed to store information indicating whether the redundant function is used or not and a defective address corresponding to a defective main word line or defective memory cell in a main memory cell array. The defective row address and the internal row adders signal are compared with each other by the programming circuit and the spare decoder, a control signal corresponding to the coincidence/non-coincidence of the compared row addresses is output, and a partial decode signal of the internal row address signal is output when the compared row addresses coincide with each other. The second partial decoder receives a control signal output from the spare decoder and outputs a partial decode signal of the internal row address signal when the control signal indicates the non-coincidence of the compared row addresses.

Abstract: First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region.

Abstract: A sense amplifier circuit characterized by comprising differential amplifying means for amplifying and outputting supplied differential input signals, and bias current control means, connected between the differential amplifying means and a ground voltage, for controlling an amount of bias current in response to the output of the differential amplifying means.

Abstract: SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

Abstract: A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.

Abstract: The external power supply voltage applied to an external power supply terminal is supplied to an internal stepdown circuit and a switch circuit. The value of the external power supply voltage is detected by an external voltage detecting circuit, and if the value is greater than a predetermined value, the internal stepdown circuit operates, the external power supply voltage is stepped down by the internal stepdown circuit and supplied to an internal circuit as an internal power supply voltage. On the other hand, if the value of the external power supply voltage is smaller than the predetermined value, the internal stepdown circuit does not operate, and instead the switch circuit operates and the external power supply voltage is supplied via the switch circuit to the internal circuit as the internal power supply voltage.

Abstract: When an address transition detector detects a transition of an address signal, it produces an address transition detect signal. The signal drives a bit line initializing circuit which in turn initializes paired bit lines, and initializes the paired output lines of a sense amplifier. At the same time, a clock signal generator generates a clock signal for a predetermined period of time in accordance with the address transition detect signal. The clock signal is supplied to the sense amplifier and a data output circuit. The sense amplifier is active during a period that the clock signal from the clock signal generator is in an effective level. The output terminal of the data output circuit is placed in a high impedance state during the period that the clock signal is in an effective level. During the other periods than the effective level period, the data output circuit produces a signal corresponding to the data as is read out of a memory cell and outputted by the sense amplifier.

Abstract: A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.