Patents by Inventor Shigeyuki Murai

Shigeyuki Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7399999
    Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: July 15, 2008
    Assignees: Sanyo Electric Co., Ltd., Gifu Sanyo Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Publication number: 20050179106
    Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Application
    Filed: April 12, 2005
    Publication date: August 18, 2005
    Applicant: Sanyo Electric Company, Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20050133814
    Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.
    Type: Application
    Filed: October 6, 2004
    Publication date: June 23, 2005
    Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Publication number: 20050116283
    Abstract: In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the present invention, a width of one end of a main wire for carrying the main current is formed wider than a width of another end of the main wire. An overall width of the main wire is formed so as to be gradually narrowed from the one end to the another end. In this way, it is possible to reduce a difference in drive voltages between a cell located in the vicinity of an electrode pad for carrying the main current and a cell located in a remote position. Resultantly, it is possible to suppress a voltage drop in the main wire and to achieve uniform operations of cells in an element.
    Type: Application
    Filed: October 20, 2004
    Publication date: June 2, 2005
    Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.
    Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
  • Patent number: 6818492
    Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: November 16, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
  • Patent number: 6786408
    Abstract: A coin-type IC card reader/writer comprises a coin-type IC card distributing unit provided in a coin-type IC card guide path, for performing the processing of reading data from the coin-type IC card and writing data to the coin-type IC card while temporarily stopping the rolling movement of the coin-type IC card, and, based on results of the processing, distributing the coin-type IC card to another coin-type IC card guide path disposed separately from the first-mentioned coin-type IC card guide path.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Nippon Conlux
    Inventors: Ryoji Yamagishi, Shigeyuki Murai
  • Patent number: 6787871
    Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 7, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Patent number: 6777277
    Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Patent number: 6682968
    Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: January 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Patent number: 6627967
    Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: September 30, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Patent number: 6617660
    Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: September 9, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Murai, Emi Fujii, Shigeharu Matsushita, Hisaaki Tominaga
  • Publication number: 20030113985
    Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.
    Type: Application
    Filed: September 8, 1999
    Publication date: June 19, 2003
    Inventors: SHIGEYUKI MURAI, EMI FUJII, SHIGEHARU MATSUSHITA, HISAAKI TOMINAGA
  • Publication number: 20030094668
    Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 22, 2003
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20030089959
    Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Application
    Filed: July 26, 2002
    Publication date: May 15, 2003
    Applicant: Sanyo Electric Company, Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20030060031
    Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Application
    Filed: July 26, 2002
    Publication date: March 27, 2003
    Applicant: Sanyo Electric Company, Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20030036252
    Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Application
    Filed: July 26, 2002
    Publication date: February 20, 2003
    Applicant: Sanyo Electric Company, Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20030025175
    Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
    Type: Application
    Filed: July 26, 2002
    Publication date: February 6, 2003
    Applicant: Sanyo Electric Company, Ltd.
    Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20020127814
    Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.
    Type: Application
    Filed: December 17, 2001
    Publication date: September 12, 2002
    Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
  • Publication number: 20020003165
    Abstract: A coin-type IC card reader/writer comprises a coin-type IC card distributing unit provided in a coin-type IC card guide path, for performing the processing of reading data from the coin-type IC card and writing data to the coin-type IC card while temporarily stopping the rolling movement of the coin-type IC card, and, based on results of the processing, distributing the coin-type IC card to another coin-type IC card guide path disposed separately from the first-mentioned coin-type IC card guide path.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 10, 2002
    Inventors: Ryoji Yamagishi, Shigeyuki Murai
  • Patent number: 5528509
    Abstract: The S-parameters of a transistor are measured at a plurality of bias points, and using a tentatively decided load resistance value, the S-parameters on the load curve are examined, based on which the power gain and input/output power characteristics are obtained to determine the optimum load. Then, by using a linear simulator, input and output circuits are designed so that the optimum load can be realized.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: June 18, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Shigeyuki Murai, Tsutomu Yamaguchi, Yasoo Harada