Patents by Inventor Shigeyuki Murai
Shigeyuki Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7399999Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.Type: GrantFiled: October 6, 2004Date of Patent: July 15, 2008Assignees: Sanyo Electric Co., Ltd., Gifu Sanyo Electronics Co., Ltd.Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
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Publication number: 20050179106Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: April 12, 2005Publication date: August 18, 2005Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20050133814Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.Type: ApplicationFiled: October 6, 2004Publication date: June 23, 2005Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
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Publication number: 20050116283Abstract: In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the present invention, a width of one end of a main wire for carrying the main current is formed wider than a width of another end of the main wire. An overall width of the main wire is formed so as to be gradually narrowed from the one end to the another end. In this way, it is possible to reduce a difference in drive voltages between a cell located in the vicinity of an electrode pad for carrying the main current and a cell located in a remote position. Resultantly, it is possible to suppress a voltage drop in the main wire and to achieve uniform operations of cells in an element.Type: ApplicationFiled: October 20, 2004Publication date: June 2, 2005Applicants: Sanyo Electric Co., Ltd., Gifu SANYO Electronics Co., Ltd.Inventors: Tetsuya Yoshida, Tetsuya Okada, Hiroaki Saito, Shigeyuki Murai, Kikuo Okada
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Patent number: 6818492Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.Type: GrantFiled: December 17, 2001Date of Patent: November 16, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
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Patent number: 6786408Abstract: A coin-type IC card reader/writer comprises a coin-type IC card distributing unit provided in a coin-type IC card guide path, for performing the processing of reading data from the coin-type IC card and writing data to the coin-type IC card while temporarily stopping the rolling movement of the coin-type IC card, and, based on results of the processing, distributing the coin-type IC card to another coin-type IC card guide path disposed separately from the first-mentioned coin-type IC card guide path.Type: GrantFiled: June 28, 2001Date of Patent: September 7, 2004Assignee: Kabushiki Kaisha Nippon ConluxInventors: Ryoji Yamagishi, Shigeyuki Murai
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Patent number: 6787871Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: GrantFiled: October 30, 2002Date of Patent: September 7, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6777277Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: August 17, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6682968Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: January 27, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6627967Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6617660Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.Type: GrantFiled: September 8, 1999Date of Patent: September 9, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeyuki Murai, Emi Fujii, Shigeharu Matsushita, Hisaaki Tominaga
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Publication number: 20030113985Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.Type: ApplicationFiled: September 8, 1999Publication date: June 19, 2003Inventors: SHIGEYUKI MURAI, EMI FUJII, SHIGEHARU MATSUSHITA, HISAAKI TOMINAGA
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Publication number: 20030094668Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030089959Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: May 15, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030060031Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: March 27, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030036252Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 20, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030025175Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20020127814Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.Type: ApplicationFiled: December 17, 2001Publication date: September 12, 2002Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
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Publication number: 20020003165Abstract: A coin-type IC card reader/writer comprises a coin-type IC card distributing unit provided in a coin-type IC card guide path, for performing the processing of reading data from the coin-type IC card and writing data to the coin-type IC card while temporarily stopping the rolling movement of the coin-type IC card, and, based on results of the processing, distributing the coin-type IC card to another coin-type IC card guide path disposed separately from the first-mentioned coin-type IC card guide path.Type: ApplicationFiled: June 28, 2001Publication date: January 10, 2002Inventors: Ryoji Yamagishi, Shigeyuki Murai
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Patent number: 5528509Abstract: The S-parameters of a transistor are measured at a plurality of bias points, and using a tentatively decided load resistance value, the S-parameters on the load curve are examined, based on which the power gain and input/output power characteristics are obtained to determine the optimum load. Then, by using a linear simulator, input and output circuits are designed so that the optimum load can be realized.Type: GrantFiled: March 17, 1994Date of Patent: June 18, 1996Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Sawai, Shigeyuki Murai, Tsutomu Yamaguchi, Yasoo Harada