Patents by Inventor Shigeyuki Okada

Shigeyuki Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090022412
    Abstract: A hierarchical coding unit hierarchically codes picked-up moving images. A storage stores moving image coded data which have been coded by the hierarchical coding unit. A hierarchical decoding unit decodes part of the moving image coded data so as to generate a moving image whose image quality is lower than the moving images. A recoding unit codes the moving image decoded by the hierarchical decoding unit. The hierarchical decoding unit decodes the moving image coded data starting from a lowest hierarchy up to a hierarchy corresponding to a specified resolution.
    Type: Application
    Filed: July 14, 2008
    Publication date: January 22, 2009
    Inventor: Shigeyuki OKADA
  • Publication number: 20080240503
    Abstract: A coding unit codes a moving image. An object detector detects an object from within a picture contained in the moving image, and generates, for each picture, object detection information containing at least the number of objects detected within an identical picture. When a codestream is generated from coded data generated by the coding unit, a stream generator describes the object detection information in a prescribed region of the codestream.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 2, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Okada, Tsugio Mori, Hideto Fujita, Akihiko Yamada
  • Publication number: 20080212719
    Abstract: A search range setting unit sets a search range to be matched with a targeted region of an image to be coded, in a reference image. A computing unit performs computation in a manner such that matching between the targeted region and a region within the search range is computed from a resolution lower than that of an original image toward the resolution of the original image over a plurality of hierarchies and the search range is narrowed. The search range setting unit sets a plurality of search ranges in the reference image in at least one of the plurality of hierarchies.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 4, 2008
    Inventors: Shigeyuki Okada, Mitsuru Suzuki
  • Publication number: 20080212886
    Abstract: A correlation evaluation unit evaluates a correction between a predetermined region in a targeted picture and a region corresponding to the region in a picture differing from the targeted picture in a temporal direction. A quantization control unit adaptively controls quantization processing for the predetermined region in the targeted picture, according to an evaluation obtained by the correlation evaluation unit. For example, when it is determined by an evaluation value obtained by the correlation evaluation unit that the correlation is weaker than a predetermined threshold value, the quantization control unit enlarges a quantization step used for quantization of the predetermined region.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 4, 2008
    Inventors: Yasuo Ishii, Mitsuru Suzuki, Shigeyuki Okada
  • Patent number: 7418146
    Abstract: Coded data are inputted from a stream analyzing unit to an entropy decoding unit. A group of peripheral information registers stores peripheral information on a target pixel for estimating a context used for arithmetic decoding of the coded data. Based on the peripheral information stored in the group of peripheral registers, a context estimation unit estimates a context and delivers the estimated context to an arithmetic decoding unit. The arithmetic decoding unit decodes the coded data based on a context label, then derives a decision and supplies the decision to an inverse quantization unit. The peripheral information stored in the group of peripheral registers is updated by a decoding result of the arithmetic decoding unit in the same cycle as the decoding.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: August 26, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsuyoshi Watanabe, Shigeyuki Okada
  • Publication number: 20080174681
    Abstract: In a digital camera, when snapshot shooting is instructed during recording of a moving image, a shot still image is temporarily pushed aside in a memory area for use in pushing aside (7a) in a frame buffer (7). A currently shooting motion image and a still image are displayed in parallel on a display (9), so that a user can confirm a content of a snapshot. The moving image continues to be recorded even during a push-aside operation. After a moving image processing is completed, the still image is processed by an image correcting circuit (4). The frame buffer (7) comprises a plurality of frame recording areas, and is shared on the occasions of a moving image processing and a still image processing. In a normal moving image processing, these areas are utilized in a cyclic manner, and when the still image is shot, any of areas will be utilized. Thereafter, the rest of areas are utilized in the cyclic manner for the moving images.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 24, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeyuki Okada, Hiroshi Hanafusa, Noriaki Kojima
  • Publication number: 20080174667
    Abstract: In a digital camera, when snapshot shooting is instructed during recording of a moving image, a shot still image is temporarily pushed aside in a memory area for use in pushing aside (7a) in a frame buffer (7). A currently shooting motion image and a still image are displayed in parallel on a display (9), so that a user can confirm a content of a snapshot. The moving image continues to be recorded even during a push-aside operation. After a moving image processing is completed, the still image is processed by an image correcting circuit (4). The frame buffer (7) comprises a plurality of frame recording areas, and is shared on the occasions of a moving image processing and a still image processing. In a normal moving image processing, these areas are utilized in a cyclic manner, and when the still image is shot, any of areas will be utilized. Thereafter, the rest of areas are utilized in the cyclic manner for the moving images.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 24, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeyuki Okada, Hiroshi Hanafusa, Noriaki Kojima
  • Publication number: 20080174668
    Abstract: In a digital camera, when snapshot shooting is instructed during recording of a moving image, a shot still image is temporarily pushed aside in a memory area for use in pushing aside (7a) in a frame buffer (7). A currently shooting motion image and a still image are displayed in parallel on a display (9), so that a user can confirm a content of a snapshot. The moving image continues to be recorded even during a push-aside operation. After a moving image processing is completed, the still image is processed by an image correcting circuit (4). The frame buffer (7) comprises a plurality of frame recording areas, and is shared on the occasions of a moving image processing and a still image processing. In a normal moving image processing, these areas are utilized in a cyclic manner, and when the still image is shot, any of areas will be utilized. Thereafter, the rest of areas are utilized in the cyclic manner for the moving images.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 24, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeyuki Okada, Hiroshi Hanafusa, Noriaki Kojima
  • Publication number: 20080174666
    Abstract: In a digital camera, when snapshot shooting is instructed during recording of a moving image, a shot still image is temporarily pushed aside in a memory area for use in pushing aside (7a) in a frame buffer (7). A currently shooting motion image and a still image are displayed in parallel on a display (9), so that a user can confirm a content of a snapshot. The moving image continues to be recorded even during a push-aside operation. After a moving image processing is completed, the still image is processed by an image correcting circuit (4). The frame buffer (7) comprises a plurality of frame recording areas, and is shared on the occasions of a moving image processing and a still image processing. In a normal moving image processing, these areas are utilized in a cyclic manner, and when the still image is shot, any of areas will be utilized. Thereafter, the rest of areas are utilized in the cyclic manner for the moving images.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 24, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeyuki Okada, Hiroshi Hanafusa, Noriaki Kojima
  • Publication number: 20080174669
    Abstract: In a digital camera, when snapshot shooting is instructed during recording of a moving image, a shot still image is temporarily pushed aside in a memory area for use in pushing aside (7a) in a frame buffer (7). A currently shooting motion image and a still image are displayed in parallel on a display (9), so that a user can confirm a content of a snapshot. The moving image continues to be recorded even during a push-aside operation. After a moving image processing is completed, the still image is processed by an image correcting circuit (4). The frame buffer (7) comprises a plurality of frame recording areas, and is shared on the occasions of a moving image processing and a still image processing. In a normal moving image processing, these areas are utilized in a cyclic manner, and when the still image is shot, any of areas will be utilized. Thereafter, the rest of areas are utilized in the cyclic manner for the moving images.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 24, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeyuki Okada, Hiroshi Hanafusa, Noriaki Kojima
  • Patent number: 7403563
    Abstract: A variable-length decoding (VLD) unit performs a variable-length decoding on an MPEG video stream. An inverse quantization (IQ) unit computes a discrete-cosine-transform (DCT) coefficient by performing an inverse quantization on results of decoding by the VLD unit. An inverse-discrete-cosine-transform (IDCT) unit carries out an IDCT for the DCT coefficients computed by the IQ unit so as to convert frequency components into the original signals. A motion-compensated-prediction (MC) unit performs a best-effort reproduction processing on received frames, during the time until the arrival of a frame serving as a reference for decoding, and returns to a normal decoding processing after the reference frame has been received.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: July 22, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Okada, Hideki Yamauchi
  • Publication number: 20080075373
    Abstract: In an image coding apparatus 100, a ROI setting unit 20 sets a ROI region in an image. An entropy coding unit 14 entropy-codes the image. A ROI information coding unit 24 encodes information for specifying the ROI region. A codestream generator 16 generates a codestream in a manner that the coded image and the coded information are explicitly included in the codestream. When a plurality of ROI regions are set in the image, the information may include a degree of priority.
    Type: Application
    Filed: October 25, 2005
    Publication date: March 27, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Okada, Kazuhiko Taketa
  • Patent number: 7333662
    Abstract: A wavelet transform is conducted on an original image (OI). At the moment when the first layer image (WI1) is generated, its LL sub-band component is recorded as an intermediate image (II) in an intermediate image memory (28). The wavelet transform is further conducted and then the third layer image (WI3) is obtained. Thereinafter, the image is processed in a quantizer and so forth and finally a coded image in JPEG 2000 is generated. On the other hand, if an image of a relatively small size is required, the intermediate image II recorded in the intermediate image memory 28 is used as a new original image (40) and coded, instead of the original image (OI).
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: February 19, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeyuki Okada
  • Publication number: 20070291131
    Abstract: As result of the diversified structure of a terminal device, the demand for data format is also diversified and there is a need to adjust a terminal to such a demand. An image coding apparatus according to the present invention uses a method complied with MPEG, as a method by which to code images, and particularly uses intra-frame coding and inter-frame coding. As an inter-frame coding method, a first mode which is a reference mode using bidirectional coding and a second mode which is a reference mode not using the bidirectional coding can be selectively set. In the case of the first mode, the bidirectional coding is not used, so that B pictures are not generated and the images are coded with I pictures and P pictures only.
    Type: Application
    Filed: January 27, 2005
    Publication date: December 20, 2007
    Inventors: Mitsuru Suzuki, Shigeyuki Okada, Shinichiro Okada
  • Publication number: 20070230658
    Abstract: In an image coding apparatus 100, a ROI setting unit 20 sets a ROI region in an image. An entropy coding unit 14 entropy-codes the image. A ROI information coding unit 24 encodes information for specifying the ROI region. A codestream generator 16 generates a codestream in a manner that the coded image and the coded information are explicitly included in the codestream. When a plurality of ROI regions are set in the image, the information may include a degree of priority.
    Type: Application
    Filed: June 13, 2007
    Publication date: October 4, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki OKADA, Kazuhiko Taketa
  • Patent number: 7272263
    Abstract: A decoding unit (12) decodes an image according to JPEG 2000. A simplifying unit (30) comprises an automatic transformer (32) which compares an elapsed time to a time limit at each stage of decoding the image and switches the decoding process to a simplified process if necessary. For instance, if the playback of a motion picture takes over 1/30 second, the simplified process, in which only low frequency components are decoded, is conducted by the automatic transformer (32).
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: September 18, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeyuki Okada
  • Patent number: 7248304
    Abstract: The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: July 24, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Okada, Kouichi Yamada, Mamoru Mukuno
  • Patent number: 7245821
    Abstract: When a reverse reproduction is instructed, an MPEG video stream is once decoded and is again recoded by an MPEG video encoder so as to generate a recoded data sequence which will be overwritten on a storage area in a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively, and then converts it to a video signal so as to be outputted to a display.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 17, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeyuki Okada
  • Patent number: 7197191
    Abstract: An SRAM is used as a pixel buffer which stores a partial image region copied from a frame buffer. A vertical filter reads a pair of target pixels arranged in a vertical direction from the pixel buffer and performs a filtering process of a discrete wavelet transform in the vertical direction. An intermediate result obtained in the filtering process is stored in a register. The vertical filter uses the intermediate result in filtering the next two pixels. A horizontal filter receives two transformed results from the vertical filter and performs a filtering process on the transformed results in the horizontal direction. The intermediate results obtained in the horizontal filtering are also stored in a register and utilized in the next filtering.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: March 27, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Okada, Kazuhiko Taketa, Hideki Yamauchi
  • Publication number: 20070064791
    Abstract: A motion vector coder performs coding on motion vectors MV0, MV1 and MV2 in the stated order. Initially, the motion vector coder receives the motion vectors MV0-MV2 from a motion vector holder. The motion vector coder codes the motion vector MV0 at the lowest layer 0. Subsequently, the motion vector coder codes (½*MV0-MV1), which is a difference between ½ of MV0 and MV1, instead of coding the motion vector MV1 at layer 1. The motion vector coder then codes (½*MV1-MV2), which is a difference between ½ of MV1 and MV2, instead of coding the motion vector MV2 at layer 2.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 22, 2007
    Inventors: Shigeyuki Okada, Yuh Matsuda, Hideki Yamauchi