Patents by Inventor Shigeyuki Okamoto

Shigeyuki Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6891872
    Abstract: A semiconductor laser device is characterized in that an angle ? of inclination formed by the side surfaces of a ridge portion and a lower part of the ridge portion is at least 70° and not more than 117°, a p-type cladding layer is made of AlX1Ga1-X1As, a first current blocking layer is made of AlX2Ga1-X2As, the distance between an emission layer and the first current blocking layer satisfies the relation of t?0.275/(1?(X2?X1)) assuming that t represents the distance, and a lower width W of the ridge portion is at least 2 ?m and not more than 5 ?m.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: May 10, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryouji Hiroyama, Yasuhiko Nomura, Koutarou Furusawa, Kunio Takeuchi, Shigeyuki Okamoto
  • Publication number: 20040252739
    Abstract: A semiconductor laser device capable of improving heat dissipativity, simplifying the fabrication process and improving the fabrication yield is obtained. This semiconductor laser device comprises a semiconductor layer formed on an emission layer while constituting a convex ridge portion, a current blocking layer consisting of a semiconductor formed to cover at least the side surfaces of the ridge portion, a first metal electrode formed to be in contact with the upper surface of the ridge portion and convex support portions arranged on both sides of the ridge portion at a prescribed interval from the ridge portion.
    Type: Application
    Filed: March 29, 2004
    Publication date: December 16, 2004
    Inventors: Kunio Takeuchi, Ryoji Hiroyama, Daijiro Inoue, Shigeyuki Okamoto, Noriaki Matsuoka, Shingo Kameyama, Kiyoshi Oota
  • Publication number: 20040245540
    Abstract: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.
    Type: Application
    Filed: January 29, 2004
    Publication date: December 9, 2004
    Inventors: Masayuki Hata, Tadao Toda, Shigeyuki Okamoto, Daijiro Inoue, Yasuyuki Bessho, Yasuhiko Nomura, Tsutomu Yamaguchi
  • Patent number: 6771676
    Abstract: A semiconductor laser device capable of improving reliability is obtained in a structure formed by mounting a semiconductor laser element on a submount (base) in a junction-down system. This semiconductor laser device comprises a first electrode layer formed on the surface of a semiconductor element including an emission layer to have a shape comprising recess portions and projection portions, a base mounted with the semiconductor element, and a plurality of low melting point metal layers provided between the first electrode layer formed on the surface of the semiconductor element and the base for bonding the first electrode layer formed on the surface of the semiconductor element and the base to each other. Thus, the plurality of low melting point metal layers easily embed clearances resulting from the shape comprising recess portions and projection portions of the surface of the semiconductor element dissimilarly to a case of employing a single low melting point metal layer.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: August 3, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kunio Takeuchi, Shigeyuki Okamoto, Ryoji Hiroyama, Yasuhiko Nomura, Daijiro Inoue
  • Patent number: 6654397
    Abstract: An n-GaAs current blocking layer is formed on a p-AlGaInP first cladding layer, on sides of a ridge portion and in a region on the upper surface of the ridge portion above a window region. Raised portions are formed in a p-GaAs cap layer in regions in the vicinity of facets, while raised regions are formed in the regions of a first electrode in the vicinity of the facets. A second electrode having a thickness larger than the height of the raised regions is formed on the region between the raised regions of the first electrode.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 25, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kunio Takeuchi, Ryoji Hiroyama, Shigeyuki Okamoto, Koji Tominaga, Yasuhiko Nomura, Daijiro Inoue
  • Publication number: 20030048818
    Abstract: A semiconductor laser device capable of improving reliability is obtained in a structure formed by mounting a semiconductor laser element on a submount (base) in a junction-down system. This semiconductor laser device comprises a first electrode layer formed on the surface of a semiconductor element including an emission layer to have a shape comprising recess portions and projection portions, a base mounted with the semiconductor element, and a plurality of low melting point metal layers provided between the first electrode layer formed on the surface of the semiconductor element and the base for bonding the first electrode layer formed on the surface of the semiconductor element and the base to each other. Thus, the plurality of low melting point metal layers easily embed clearances resulting from the shape comprising recess portions and projection portions of the surface of the semiconductor element dissimilarly to a case of employing a single low melting point metal layer.
    Type: Application
    Filed: September 5, 2002
    Publication date: March 13, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kunio Takeuchi, Shigeyuki Okamoto, Ryoji Hiroyama, Yasuhiko Nomura, Daijiro Inoue
  • Publication number: 20020024985
    Abstract: An n-GaAs current blocking layer is formed on a p-AlGaInP first cladding layer, on sides of a ridge portion and in a region on the upper surface of the ridge portion above a window region. Raised portions are formed in a p-GaAs cap layer in regions in the vicinity of facets, while raised regions are formed in the regions of a first electrode in the vicinity of the facets. A second electrode having a thickness larger than the height of the raised regions is formed on the region between the raised regions of the first electrode.
    Type: Application
    Filed: August 30, 2001
    Publication date: February 28, 2002
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kunio Takeuchi, Ryoji Hiroyama, Shigeyuki Okamoto, Koji Tominaga, Yasuhiko Nomura, Daijiro Inoue
  • Patent number: 5955926
    Abstract: A plurality of FETs have their respective gates connected to each other through a first line and their respective drains connected to each other through a second line. A gate bias is applied to the gate of each FET through the first line and a drain bias is applied to the drain of each FET through the second line. A first matching circuit includes first capacitors connected to the signal path, inductors each connected between one end of each first capacitor and the ground potential, and second capacitors each connected between the other end of each first capacitor and the ground potential. The second matching circuit includes first capacitors each connected to the signal path, second capacitors each connected between one end of each first capacitor and the ground potential, and inductors each connected between the other end of each first capacitor and the ground potential.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: September 21, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Shigeyuki Okamoto