Patents by Inventor SHIH-AN HO
SHIH-AN HO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220115243Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
-
Patent number: 11292101Abstract: A chemical mechanical polishing apparatus is provided. The chemical mechanical polishing apparatus includes a polishing pad, a pad conditioner, a measurement tool, and a controller. The polishing pad is provided in a processing chamber for polishing a wafer placed on the polishing surface of the polishing pad. The pad conditioner is configured to condition the polishing surface. The measurement tool is provided in the processing chamber and configured to measure the downward force of the pad conditioner. The controller is coupled to the pad conditioner and the measurement tool, and is configured to adjust the downward force of the pad conditioner in response to an input from the measurement tool.Type: GrantFiled: February 26, 2018Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
-
Patent number: 11249658Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.Type: GrantFiled: September 27, 2019Date of Patent: February 15, 2022Assignee: Rambus, Inc.Inventors: Shih-ho Wu, Christopher Haywood
-
Patent number: 11251063Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.Type: GrantFiled: October 7, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai
-
Patent number: 11239092Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.Type: GrantFiled: April 27, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
-
Publication number: 20210312965Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Patent number: 11094554Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen. The wafer includes a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The method also includes polishing the wafer using a first operation to thin down the metal layer. The first operation has a first polishing selectivity of the metal layer to the dielectric layer. The method further includes polishing the wafer using a second operation to further thin down the metal layer until the dielectric layer is exposed. The second operation has a second polishing selectivity of the metal layer to the dielectric layer. The second polishing selectivity is different from the first polishing selectivity. The first operation and the second operation are performed in-situ on the polishing platen.Type: GrantFiled: March 31, 2017Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Ho Lin, Jen-Chieh Lai, Jheng-Si Su, Zhi-Sheng Hsu, Po-Ting Huang
-
Publication number: 20210216826Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.Type: ApplicationFiled: March 27, 2020Publication date: July 15, 2021Applicants: Acer Incorporated, National Yang-Ming UniversityInventors: Cheng-Tien Hsieh, Chun-Hsien Yu, Shih-Ho Huang, Meng-Che Cheng, Kun-Hsien Chou, Ching-Po Lin, Liang-Kung Chen
-
Patent number: 11043251Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: GrantFiled: September 10, 2019Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Patent number: 11038077Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.Type: GrantFiled: March 4, 2019Date of Patent: June 15, 2021Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Po-Han Lee, Chien-Min Lin, Yi-Rong Ho
-
Publication number: 20210066379Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.Type: ApplicationFiled: November 17, 2020Publication date: March 4, 2021Inventors: Yen-Shih HO, Tsang-Yu LIU, Po-Han LEE
-
Publication number: 20210060728Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
-
Publication number: 20210028049Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.Type: ApplicationFiled: October 7, 2020Publication date: January 28, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jheng-Si SU, Yu-Chen WEI, Chih-Yuan YANG, Shih-Ho LIN, Jen-Chieh LAI
-
Patent number: 10896099Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.Type: GrantFiled: October 10, 2018Date of Patent: January 19, 2021Assignee: RAMBUS INCInventors: Shih-ho Wu, Christopher Haywood
-
Patent number: 10843307Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: GrantFiled: November 9, 2018Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
-
Patent number: 10804133Abstract: A method for transporting an article used in semiconductor fabrication is provided. The method includes moving a first transporter next to an article to have the article faces a plurality of gas holes formed on the first transporter; suspending the article with the first transporter in a non-contact manner by providing a flow of gas through the gas holes of the first transporter; and transferring the article with the first transporter while the flow of gas is continuously provided.Type: GrantFiled: May 30, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai
-
Publication number: 20200258758Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
-
Publication number: 20200238473Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
-
Publication number: 20200176041Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: ApplicationFiled: September 10, 2019Publication date: June 4, 2020Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Publication number: 20200149862Abstract: A localization and attitude estimation method using magnetic fields includes the following steps. First, in three-dimensional coordinates, at least three magnetic landmarks arbitrarily disposed around a moving carrier are selected, wherein any two of the at least three magnetic landmarks have different magnetic directions. One set of at least five tri-axes magnetic sensors is used to sense the magnetic fields of the at least three magnetic landmarks. Three magnetic components on three axes of a current position of each of the tri-axes magnetic sensors are respectively generated by a demagnetization method. Five non-linear magnetic equations are solved to obtain position information and magnetic moment information of the at least three magnetic landmarks in the three-dimensional coordinates. Position vectors and attitude vectors of the set of at least five tri-axes magnetic sensors in a three-dimensional space are estimated based on tri-axes magnetic moment vectors of the magnetic landmarks.Type: ApplicationFiled: December 27, 2018Publication date: May 14, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Wen Luo, Shih-Ho Hsieh, Jwu-Sheng Hu