Patents by Inventor Shih-An Yu

Shih-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240357740
    Abstract: Provided is a micro-roughened electrodeposited copper foil, which comprises a micro-rough surface and multiple copper nodules. The micro-roughened electrodeposited copper foil has an Sdr of 0.01 to 0.08. With the surface characteristics, the electron path distance can be shortened, such that the micro-roughened electrodeposited copper foil can reduce the insertion loss of the copper clad laminate at high frequencies and have the desired peel strength.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Yun-Hsing SUNG, Shih-Shen Lee, Hung-Wei Hsu, Chun-Yu Kao
  • Publication number: 20240355660
    Abstract: Air curtain devices can reduce defects on semiconductor wafers when implemented on a track equipped with robotic wafer transport. The air curtain devices can be added to one or more processing devices arranged along the track to prevent defects from landing on wafer surfaces. For example, the air curtain devices can prevent volatile organic solvent mist from drifting towards processing devices on the track and preventing contamination via a wafer transport system.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih LIAO, Shih-Yu TSENG
  • Patent number: 12125783
    Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Shih Wei Bih, Yen-Yu Chen
  • Publication number: 20240347642
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Shih-Hao Lin, Chong-De Lien, Chih-Chuan Yang, Chih-Yu Hsu, Ming-Shuan Li, Hsin-Wen Su
  • Publication number: 20240347626
    Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: TSUNG-HUA YANG, CHENG-BO SHU, CHIA-TA HSIEH, PING-CHENG LI, PO-WEI LIU, SHIH-JUNG TU, TSUNG-YU YANG, YUN-CHI WU, YU-WEN TSENG
  • Patent number: 12120816
    Abstract: Provided is a micro-roughened electrodeposited copper foil, which comprises a micro-rough surface and multiple copper nodules. The micro-roughened electrodeposited copper foil has an Rlr value of 1.05 to 1.60, or an Sdr of 0.01 to 0.08. With the surface characteristics, the electron path distance can be shortened, such that the micro-roughened electrodeposited copper foil can reduce the insertion loss of the copper clad laminate at high frequencies and have the desired peel strength.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 15, 2024
    Assignee: CO-TECH DEVELOPMENT CORP.
    Inventors: Yun-Hsing Sung, Shih-Shen Lee, Hung-Wei Hsu, Chun-Yu Kao
  • Patent number: 12118653
    Abstract: A system, method, and computer program product are provided for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: October 15, 2024
    Assignee: MediaTek Inc.
    Inventors: Po-Yu Huang, Shih-Chin Lin, Jen-Jung Cheng, Tu-Hsiu Lee
  • Patent number: 12113122
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Publication number: 20240333155
    Abstract: A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Inventors: WEN-HAU YANG, YEN-TING LIN, CHUN-YU LUO, SHIH-CHIEH CHEN, HUNG-HSUAN CHENG
  • Publication number: 20240332069
    Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Y.T. Chen, Da-Wei Lin
  • Patent number: 12108691
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: October 1, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chich-Neng Chang, Da-Jun Lin, Shih-Wei Su, Fu-Yu Tsai, Bin-Siang Tsai
  • Patent number: 12105317
    Abstract: An electronic device includes a light guide plate, a plurality of light sources, a sealant frame and at least an optical film. The light guide plate includes a first end portion and a second end portion opposite to each other. The plurality of light sources are disposed adjacent to the second end portion and are arranged along the first direction. The sealant frame is disposed adjacent to the first end portion. One of the at least an optical film includes a body portion and a lug portion connected to the body portion, and the lug portion is fixed on the sealant frame. The body portion includes a first side adjacent to the sealant frame and, in a second direction, a shortest distance between the first side and the sealant film is in a range of 0 mm to 0.4 mm.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: October 1, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Shih-Ching Hsu, Hsin-Hung Chen, Chia-Yu Chung
  • Publication number: 20240316179
    Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).
    Type: Application
    Filed: May 13, 2024
    Publication date: September 26, 2024
    Inventors: Chi-Huey WONG, Hsin-Yu LIAO, Shih-Chi WANG, Yi-An KO, Kuo-I LIN, Che MA, Ting-Jen CHENG
  • Publication number: 20240313119
    Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20240308886
    Abstract: This invention demonstrates with practical examples that the PVA-immobilized microbial gel bead technology can protect microorganisms and can perfectly match the electrolysis that inhibits microorganisms. For instance: (1) After nitrification in the PVA gel bead system, nitrate-nitrogen can be removed through electrolysis. (2) In the case of high COD (Chemical Oxygen Demand) or organic nitrogen concentration, the PVA gel bead system can be used for degradation or hydrolysis, followed by rapid electrolytic removal of refractory COD and ammonia-nitrogen. (3) By integrating the PVA gel bead system with the electrolysis system in parallel, the rapid response of electrolysis can be utilized to swiftly adjust the overall performance of water treatment. (4) For low-salinity water body, the “PVA Gel Bead Energization” treatment can be applied, where the electrodes are directly inserted into the bioreactor.
    Type: Application
    Filed: August 15, 2023
    Publication date: September 19, 2024
    Inventors: Shih-Wei Huang, Sz-Chwun Hwang, Z-Yu Huang
  • Publication number: 20240310429
    Abstract: An electrical connector includes an outer shell, an insulating element, and a central conductive terminal. The outer shell includes a mounting hole. The insulating element is installed in the mounting hole. The central conductive terminal includes a first fitting portion, a second fitting portion and an intermediate portion. When a signal is transmitted in the first fitting portion, it encounters an impedance having a first impedance value. When the signal is transmitted in the second fitting portion, it encounters an impedance having a second impedance value. The intermediate portion includes an impedance transition area. When the signal is transmitted in the impedance transition area, it encounters an impedance having a gradually changing third impedance value. The first impedance value, the third impedance value and the second impedance value generally have a smooth transition. An adapter and a test device having the electrical connector are disclosed.
    Type: Application
    Filed: November 27, 2023
    Publication date: September 19, 2024
    Applicant: Luxshare Precision Industry Company Limited
    Inventors: Chien-Yu HSU, Ruey-Ting LIAO, Shih-Tung LIN, Chi-Wei LIN
  • Patent number: 12094184
    Abstract: Feature descriptor matching is reformulated into a graph-matching problem. Keypoints from a query image and a reference image are initially matched and filtered based on the match. For a given keypoint, a feature graph is constructed based on neighboring keypoints surrounding the given keypoint. The feature graph is compared to a corresponding feature graph of a reference image for the matched keypoint. Relocalization data is obtained based on the comparison.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: September 17, 2024
    Assignee: Apple Inc.
    Inventors: Chen Huang, Seyed Hesameddin Najafi Shoushtari, Frankie Lu, Shih-Yu Sun, Joshua M. Susskind
  • Publication number: 20240304461
    Abstract: A ceramic submount for a semiconductor device and a method for manufacturing the same are provided. The ceramic submount includes a ceramic core board, an electrode layer, and a solder unit. The electrode layer is disposed on one side of the ceramic core board. The solder unit includes a buffer containing layer and a soldering layer. A cross-section of the solder unit has an inversed-trapezoid shape. The buffer containing layer is disposed on a surface of the electrode layer. A receiving space is concavely formed on a top surface of the buffer containing layer, and the soldering layer is filled in the receiving space. The buffer containing layer surrounds the soldering layer.
    Type: Application
    Filed: December 26, 2023
    Publication date: September 12, 2024
    Inventors: CHENG-HUNG SHEN, SHIH-HAN WU, JHIH-WEI LAI, JIAN-YU SHIH, MING-YEN PAN, CHIA-SHUAI CHANG
  • Publication number: 20240304521
    Abstract: A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.
    Type: Application
    Filed: September 12, 2023
    Publication date: September 12, 2024
    Inventors: Kuan Yu CHEN, Chun-Yen LIN, Wei-Cheng TZENG, Wei-Cheng LIN, Shih-Wei PENG, Jiann-Tyng TZENG
  • Patent number: 12087079
    Abstract: A display apparatus and an fingerprint sensing method thereof are provided. A display panel of the display apparatus has a pixel circuit array, an in-display touch sensor array, and an in-display fingerprint sensor array. A driving circuit drives the in-display fingerprint sensor array to read a fingerprint image. A current display frame period is divided into a plurality of unit periods, each of the unit periods includes at least one fingerprint sensing period and one or both of a display driving period and a touch sensing period. The driving circuit resets a current fingerprint sensor in the in-display fingerprint sensor array during a first fingerprint sensing period among these fingerprint sensing periods of the first display frame period. The driving circuit reads a sensing result of the current fingerprint sensor during a second fingerprint sensing period succeeding to the first fingerprint sensing period.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: September 10, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Cho-Hsuan Jhang, Chao-Yu Meng, Shih-Cheng Chen, Chih-Peng Hsia