Patents by Inventor Shih-Chang Chen

Shih-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11954527
    Abstract: A resource allocation method comprises using resources with a used resource quantity of a machine learning system to execute a first experiment which has a first minimum resource demand, receiving an experiment request associated with a target dataset, deciding a second experiment according to the target dataset, deciding a second minimum resource demand of the second experiment, allocating resources with a quantity equal to the second minimum resource demand for an execution of the second experiment when a total resource quantity of the machine learning system meets a sum of the first minimum resource demand and the second minimum resource demand and a difference between the total resource quantity and the used resource quantity meets the second minimum resource demand, determining that the machine learning system has an idle resource, and selectively allocating said the idle resource for at least one of the first experiment and the second experiment.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 9, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Chang Chen, Yi-Chin Chu, Yi-Fang Lu
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11935969
    Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-Chang Lee, Shiuan-Leh Lin, I-Hung Chen, Chu-Jih Su, Chao-Shun Huang
  • Publication number: 20240088289
    Abstract: A transistor includes: a substrate; a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section; a first drain and a second drain; a first source and a second source; a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.
    Type: Application
    Filed: February 19, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Chao Shen, Shih-Chang Chen
  • Patent number: 11929287
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao
  • Publication number: 20240077804
    Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Hsun LIN, Chien-Cheng CHEN, Shih Ju HUANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20240071523
    Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kun-Tse Lee, Han-Sung Chen, Shih-Chang Huang
  • Patent number: 11916122
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
  • Patent number: 11889764
    Abstract: A piezoelectric actuator includes a square suspension plate, an outer frame, a plurality of brackets and a square piezoelectric ceramic plate. The outer frame is arranged around the suspension plate. A second surface of the outer frame and a second surface of the suspension plate are coplanar with each other. Each of the plurality of brackets has two ends, a first end is perpendicular to and connected with the suspension plate, and a second end is perpendicular to and connected with the outer frame for elastically supporting the suspension plate. Each bracket has a length in a range between 1.22 mm and 1.45 mm and a width in a range between 0.2 mm and 0.6 mm. A length of the piezoelectric ceramic plate is not larger than a length of the suspension plate. The piezoelectric ceramic plate is attached on a first surface of the suspension plate.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 30, 2024
    Assignee: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Che-Wei Huang, Chi-Feng Huang, Yung-Lung Han, Chun-Yi Kuo, Wei-Ming Lee
  • Publication number: 20240007208
    Abstract: An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.
    Type: Application
    Filed: October 5, 2022
    Publication date: January 4, 2024
    Inventors: Shih-Chang CHEN, Chih-Wei CHANG, Chun-Chi YU
  • Publication number: 20230418495
    Abstract: Techniques for persisting user data across secure shell instances are provided. A method includes receiving a first request from a session manager service to establish a connection to a secure shell instance and restore a user block volume with corresponding backup user data. The method may include reserving an empty block volume. The method may also include transmitting a backup data identifier associated with the corresponding backup user data to a backup service and receiving the corresponding backup user data from the backup service. The method may further include providing the corresponding backup user data to the empty block volume to create a restore volume and transmitting a restore volume identifier corresponding to a data center identifier to the session manager service. The method may include receiving a second request to attach the restore volume to a reserved instance, the second request being received from the session manager service.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Applicant: Oracle International Corporation
    Inventors: Christopher S. Kasso, Peter Grant Gavares, Shih-Chang Chen, Devasena Kiruba Sagar, Michael William Gilbode
  • Patent number: 11855010
    Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shan-Yu Huang, Shih-Chang Chen, Hsiao-Wen Chung, Yilun Chen, Huang-Sheng Lin
  • Patent number: 11848802
    Abstract: The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Peng-Fei Lin, Chen-Yuan Chang, Shih-Chang Chen
  • Publication number: 20230402406
    Abstract: An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventors: Shan-Yu Huang, Shih-Chang Chen, Yilun Chen, Huang-Sheng Lin
  • Publication number: 20230386972
    Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 30, 2023
    Inventors: Jen-Yuan CHANG, Chia-Ping LAI, Shih-Chang CHEN, Tzu-Chung TSAI, Chien-Chang LEE
  • Publication number: 20230381056
    Abstract: A changeable massage device includes a main body, a position limiter, and a control member. The main body includes a combination part and a body part. The position limiter is slidably disposed on the combination member and has a limiting recess. The position limiter moves between an opening and a locking position. The control member is between the main body and the position limiter. The control member has an operation part and a connection part movably connected with the body part. When the position limiter is at the opening position, the operation part is pressed and engaged in the limiting recess, whereby a roller is mounted around or detached from the main body. When the position limiter is pressed to change to the locking position, the operation part leaves the limiting recess to abut against the position limiter, and the roller is fixed to the main body.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventor: SHIH-CHANG CHEN
  • Patent number: 11789627
    Abstract: Techniques for persisting user data across secure shell instances are provided. A method includes receiving a first request from a session manager service to establish a connection to a secure shell instance and restore a user block volume with corresponding backup user data. The method may include reserving an empty block volume. The method may also include transmitting a backup data identifier associated with the corresponding backup user data to a backup service and receiving the corresponding backup user data from the backup service. The method may further include providing the corresponding backup user data to the empty block volume to create a restore volume and transmitting a restore volume identifier corresponding to a data center identifier to the session manager service. The method may include receiving a second request to attach the restore volume to a reserved instance, the second request being received from the session manager service.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: October 17, 2023
    Assignee: Oracle International Corporation
    Inventors: Christopher S. Kasso, Peter Grant Gavares, Shih-Chang Chen, Devasena Kiruba Sagar, Michael William Gilbode
  • Publication number: 20230307038
    Abstract: A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 28, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Shih-Chang Chen, Chih-Wei Chang, Chun-Chi Yu