Abstract: A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: An exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas includes: a main exhaust pipe above the semiconductor manufacturing equipment and having a top surface on a first side and a bottom surface on a second side, a first branch pipe connected to a source of a gas mixture containing the hazardous gas on the second side and connected to the main exhaust pipe through the top surface, a second branch pipe connected to a gas box on the second side and connected to the main exhaust pipe through the bottom surface, and a detector on the second branch pipe configured to detect presence of the hazardous gas and downstream to the gas box. The first and the second branch pipes are connected to the main exhaust pipe at a first location and a second location, respectively. The first location is more upstream than the second location.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: The disclosure provides a liquid-cooling device and an electronic device. The liquid-cooling device includes an accommodation housing and a liquid-cooling assembly. The accommodation housing has an accommodation structure. The liquid-cooling assembly includes at least one liquid-cooling heat exchanger, a cold plate and a tubing. The at least one liquid-cooling heat exchanger is located in the accommodation structure. The cold plate is covered on the accommodation housing and covers the accommodation structure. The tubing is connected to the at least one liquid-cooling heat exchanger and penetrates through the cold plate.

Abstract: Methods for breaking-in new polishing pads of a double-side polishing apparatus for polishing substrates such as single crystal silicon wafers are disclosed. The methods may involve contacting the new polishing pads with a conditioning substrate such as a substate that includes diamonds at the surface of the substrate. Conditioning methods may also involve contacting the new polishing pad with sacrificial substrates.

Abstract: A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Abstract: A gait evaluating system including a processor is provided. The processor identifies whether a gait type of the user belongs to a normal gait, a non-neuropathic gait or a neuropathic gait based on step feature values of a user and walking limb feature values of the user. In response to that the gait type of the user belongs to the non-neuropathic gait, the processor controls the display panel to display a first auxiliary information, a second auxiliary information, and a third auxiliary information. The first auxiliary information indicates a potential sarcopenia of the user. The second auxiliary information indicates a dietary guideline for muscle building and muscle strengthening. The third auxiliary information shows a motion instruction video for regaining or maintaining muscle strength of the user.

Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

Abstract: The present disclosure provides a semiconductor light-emitting device and a semiconductor light-emitting component. The semiconductor light-emitting device includes a substrate, a first semiconductor contact layer, a semiconductor light-emitting stack including an active layer, a first-conductivity-type contact structure, a second semiconductor contact layer, a second-conductivity-type contact structure and a first electrode pad. The first-conductivity-type contact structure is electrically connected to the first semiconductor contact layer. The second-conductivity-type contact structure is electrically connected to the second semiconductor contact layer. The first-conductivity-type contact structure has a first bottom surface and a first top surface, and the active layer has a second bottom surface and a second top surface.

Abstract: The present disclosure discloses a memory signal calibration apparatus and a memory signal calibration method. A gating circuit generates a data strobe enablement setting signal according to a setting control signal, generates an enabling state of the data strobe enablement signal and performs gating on a data strobe signal according to the enabling state to generate a gated data strobe signal.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.