Abstract: A semiconductor device includes a substrate, a semiconductor component and a heat dissipation component. The semiconductor component is disposed on the substrate. The heat dissipation component is disposed on the substrate and having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity.

Abstract: Disclosed are a semiconductor structure and a manufacturing method of a semiconductor structure. In one embodiment, the semiconductor structure includes a first semiconductor element, a second semiconductor element, a heat dissipation element and a gap-filling material. The second semiconductor element is on the first semiconductor element. The heat dissipation element is on the first semiconductor element and spaced apart from the second semiconductor element by a gap. The gap-filling material is filled in the gap between the second semiconductor element and the heat dissipation element.

Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.

Abstract: A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.

Abstract: Packaged semiconductor devices including heat-dissipating structures and methods of forming the same are disclosed. In an embodiment, a semiconductor package includes a semiconductor die including a substrate, a front-side interconnect structure on a front-side of the substrate, and a backside interconnect structure on a backside of the substrate opposite the front-side interconnect structure; a support die disposed on the front-side interconnect structure; a heat-dissipating structure on the support die, the heat-dissipating structure being thermally coupled to the semiconductor die and the support die; a redistribution structure on the backside interconnect structure opposite the substrate, the redistribution structure being electrically coupled to the semiconductor die; and an encapsulant on the redistribution structure and adjacent to side surfaces of the semiconductor die, the support die, and the heat-dissipating structure.

Abstract: A method includes forming a first dielectric layer on a first wafer, and forming a first bond pad penetrating through the first dielectric layer. The first wafer includes a first semiconductor substrate, and the first bond pad is in contact with a first surface of the first semiconductor substrate. The method further includes forming a second dielectric layer on a second wafer and forming a second bond pad extending into the second dielectric layer. The second wafer includes a second semiconductor substrate. The first wafer is sawed into a plurality of dies, with the first bond pad being in a first die in the plurality of dies. The first bond pad is bonded to the second bond pad.

Abstract: A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

Abstract: A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.

Abstract: A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.