Patents by Inventor Shih-Chang Liu

Shih-Chang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming a split-gate flash memory cell device with a low power logic device
    Patent number: 9741728
    Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chang-Ming Wu, Shih-Chang Liu
  • Self-aligned split gate flash memory
    Patent number: 9741868
    Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Tai Tseng, Chang-Ming Wu, Shih-Chang Liu
  • Recessed salicide structure to integrate a flash memory device with a high ?, metal gate logic device
    Patent number: 9735245
    Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry Hak-Lay Chuang, Wei Cheng Wu, Shih-Chang Liu, Ya-Chen Kao
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170229646
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a planar bottom barrier layer over and in contact with the Nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (N+1)th metal layer over the electrode. N is a positive integer. A manufacturing method for the semiconductor structure is also provided.
    Type: Application
    Filed: April 10, 2017
    Publication date: August 10, 2017
    Inventors: CHUNG-YEN CHOU, CHING-PEI HSIEH, SHIH-CHANG LIU
  • Leakage resistant RRAM/MIM structure
    Patent number: 9728719
    Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai
  • Method for preventing floating gate variation
    Patent number: 9728545
    Abstract: A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Ming Wu, Shih-Chang Liu
  • SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170222128
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
    Type: Application
    Filed: May 10, 2016
    Publication date: August 3, 2017
    Inventors: FU-TING SUNG, CHUNG-CHIANG MIN, YUAN-TAI TSENG, CHERN-YOW HSU, SHIH-CHANG LIU
  • Techniques to avoid or limit implant punch through in split gate flash memory devices
    Patent number: 9716097
    Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Ming Wu, Shih-Chang Liu, Sheng-Chieh Chen, Yung-Chang Chang
  • SEMICONDUCTOR STRUCTURE, ELECTRODE STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20170207385
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: CHUNG-YEN CHOU, FU-TING SUNG, YAO-WEN CHANG, SHIH-CHANG LIU
  • Capacitor structure and method of manufacturing the same
    Patent number: 9711508
    Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu
  • Semiconductor structure, electrode structure and method of forming the same
    Patent number: 9711713
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
  • REVERSED STACK MTJ
    Publication number: 20170194559
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20170194557
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
    Type: Application
    Filed: May 19, 2016
    Publication date: July 6, 2017
    Inventors: HARRY-HAK-LAY CHUANG, SHIH-CHANG LIU, CHERN-YOW HSU, KUEI-HUNG SHEN
  • Magnetoresistive Random Access Memory Structure and Method of Forming the Same
    Publication number: 20170186946
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.
    Type: Application
    Filed: March 10, 2017
    Publication date: June 29, 2017
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Asymmetric formation approach for a floating gate of a split gate flash memory structure
    Patent number: 9691883
    Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Yuan-Tai Tseng, Chang-Ming Wu, Shih-Chang Liu
  • Magnetoresistive random access memory cell and fabricating the same
    Patent number: 9685604
    Abstract: A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Shih-Chang Liu
  • Semiconductor structure for flash memory cells and method of making same
    Patent number: 9679979
    Abstract: Semiconductor structures are presented. An exemplary semiconductor structure comprises a common source region having a sawtooth profile, and a flat erase gate disposed above the common source region. Methods of making semiconductor structures are also presented. An exemplary method comprises forming a plurality of trenches in a substrate thereby forming a plurality of active regions; forming a common source region in the substrate in a direction perpendicular to the active regions. The exemplary method further comprises, after forming the common source region, forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features, and forming an erase gate on the dielectric feature.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Chang-Ming Wu, Shih-Chang Liu, Wei Cheng Wu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
  • Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY
    Publication number: 20170162590
    Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu, Chang-Ming Wu
  • Semiconductor arrangement and formation thereof
    Patent number: 9673194
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Shih-Chang Liu, Ming Chyi Liu
  • Semiconductor device structure and method for forming the same
    Patent number: 9673204
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Ming Wu, Tsung-Hsueh Yang, Chung-Chiang Min, Shih-Chang Liu