Abstract: A display panel includes an array substrate and light emitting elements. The array substrate includes a substrate, pad groups, and a retaining wall structure. The substrate has a surface. The surface has a corner, and the corner has two edges connected to each other. The pad groups are disposed on the surface and include a first pad groups located at the corner. The retaining wall structure is disposed on the surface and is located at the corner, and is located between the first pad groups and the two edges of the corner. The retaining wall structure and at least one film layer of the pad groups are formed by patterning the same film layer. The light emitting elements are disposed on the pad groups, respectively.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.