Patents by Inventor Shih-Chen Wang
Shih-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240383100Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
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Publication number: 20240359288Abstract: A method of using a polishing pad includes applying a slurry in a first region of the polishing pad. The method further includes spreading the slurry across the first region of the polishing pad at a first rate. The method further includes spreading the slurry across a second region at a second rate different from the first rate, wherein the second region is farther from a center of the polishing pad than the first region. The method further includes spreading the slurry across a third region at a third rate different from the second rate, wherein the second region is between the third region and the first region.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: ChunHung CHEN, Jung-Yu LI, Sheng-Chen WANG, Shih-Sian HUANG
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Patent number: 12070833Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves. The method further includes spreading the slurry across a second region, surrounding the first region of the polishing pad at a second rate different from the first rate, wherein the second region includes a plurality of second grooves. The method further includes spreading the slurry across a third region, surrounding the second region of the polishing pad at a third rate less than the first rate and the second rate, wherein the third region includes a plurality of third grooves.Type: GrantFiled: June 26, 2023Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chunhung Chen, Jung-Yu Li, Sheng-Chen Wang, Shih-Sian Huang
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Publication number: 20240259779Abstract: A user equipment (UE) device performs fast network camping when multiple SIMs of the UE device are out of service. A first software stack begins scanning for available networks and finds an available network at a frequency X. The first software stack decodes system information received from the available network at frequency X and determines that the available network is mapped to the SIM associated with a second software stack of the UE device. The first software stack signals the second software stack that an available network is mapped to the SIM associated with the second software stack at frequency X. In response to receiving the signal, the second software stack sends an attach request to the available network and completes a network attach procedure.Type: ApplicationFiled: December 20, 2022Publication date: August 1, 2024Inventors: Edison Chen, Shih-Che Chou, Chih-Cheng Wang, Hsueh-Feng Hsieh
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Patent number: 12046754Abstract: An aluminum battery negative electrode structure includes an aluminum foil and a coating layer. The coating layer is arranged on the aluminum foil. A material of the coating layer includes a high specific surface area carbon material. A specific surface area of the high specific surface area carbon material ranges from 500 m2/g to 3,000 m2/g.Type: GrantFiled: November 2, 2022Date of Patent: July 23, 2024Assignee: APh ePower Co., Ltd.Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Yi Hsiu Wang, Wei-An Chen
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Patent number: 11929434Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: GrantFiled: April 15, 2022Date of Patent: March 12, 2024Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Publication number: 20220246758Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: ApplicationFiled: April 15, 2022Publication date: August 4, 2022Applicant: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Patent number: 11398259Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.Type: GrantFiled: February 24, 2021Date of Patent: July 26, 2022Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Hsin Chen, Chun-Yuan Lo, Shih-Chen Wang, Tsung-Mu Lai
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Patent number: 11335805Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: GrantFiled: September 8, 2020Date of Patent: May 17, 2022Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Patent number: 11164880Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.Type: GrantFiled: March 29, 2019Date of Patent: November 2, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chih-Hsin Chen, Wei-Ren Chen
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Publication number: 20210287746Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.Type: ApplicationFiled: February 24, 2021Publication date: September 16, 2021Inventors: Chih-Hsin CHEN, Chun-Yuan LO, Shih-Chen WANG, Tsung-Mu LAI
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Patent number: 11063772Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.Type: GrantFiled: June 6, 2018Date of Patent: July 13, 2021Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
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Publication number: 20210074855Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: ApplicationFiled: September 8, 2020Publication date: March 11, 2021Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Patent number: 10642579Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.Type: GrantFiled: May 25, 2018Date of Patent: May 5, 2020Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Hsin Chen, Shih-Chen Wang
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Publication number: 20200006508Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.Type: ApplicationFiled: March 29, 2019Publication date: January 2, 2020Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
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Publication number: 20190164981Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.Type: ApplicationFiled: June 6, 2018Publication date: May 30, 2019Inventors: Chih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
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Publication number: 20190115076Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.Type: ApplicationFiled: May 25, 2018Publication date: April 18, 2019Inventors: Chih-Hsin CHEN, Shih-Chen Wang
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Patent number: 10224108Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.Type: GrantFiled: January 3, 2018Date of Patent: March 5, 2019Assignee: EMEMORY TECHNOLOGY INC.Inventors: Wen-Hao Ching, Shih-Chen Wang
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Patent number: 10181342Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.Type: GrantFiled: November 3, 2017Date of Patent: January 15, 2019Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
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Publication number: 20180315462Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.Type: ApplicationFiled: November 3, 2017Publication date: November 1, 2018Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao