Abstract: A system having a Reconfigurable ReflectArray (RRA) structure includes a radiation layer and a control layer. The radiation layer includes at least one P-Intrinsic-N (P-I-N) diode and a plurality of reconfigurable reflective units. At least one part of the reconfigurable reflective units is electrically connected to the at least one P-I-N diode. The control layer includes at least one switch element and at least one control unit. The at least one switch element is electrically connected to the radiation layer. The at least one control unit is electrically connected to the at least one switch element. The number of the reconfigurable reflective units is different from the number of the at least one switch element.

Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.

Abstract: A method includes attaching a second workpiece to a first workpiece, performing a first plasma etching process to a back side of the first workpiece to form a first trench, and forming a first backside conductive feature in the first trench. The first workpiece includes a first transistor including a source/drain (S/D) feature, a second transistor adjacent to the first transistor and comprising a gate structure, a diode, and an interconnect structure including a plurality of metal lines and vias. A first interconnect layer of the interconnect structure includes a metal line electrically coupled to the gate structure and the S/D feature. The second workpiece includes a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate disposed over the first dielectric layer. The metal feature is electrically coupled to the gate structure by the diode and the plurality of metal lines and vias.

Abstract: A semiconductor device includes a substrate, an active structure, a first dielectric layer and a second dielectric layer. The active structure is formed on the substrate and includes an active channel sheet, wherein the active channel sheet has a first lateral surface. The first dielectric layer is formed above the active structure and has a recess, wherein the recess is recessed with respect to the first lateral surface of the active channel sheet. The second dielectric layer is formed within the recess and has a dielectric constant, wherein the dielectric constant is less than 3.9.

Abstract: A reconfigurable intelligent surface includes a radiant layer, a sensing feeding circuit layer, a processing layer and a controlling circuit layer. The radiant layer includes at least two antennas and a plurality of reflecting units. Each of the at least two antennas is configured for sensing a polarization, a frequency or a direction angle of an incident electromagnetic wave. The reflecting units are arranged to form a reflecting surface. The sensing feeding circuit layer is signally connected to the antennas. The processing layer is signally connected to the sensing feeding circuit layer, and the processing layer is configured to produce a controlling signal corresponding thereto. The controlling circuit layer is signally connected to the radiant layer and the processing layer, wherein the controlling circuit layer receives the controlling signal and controls the reflecting units according to the controlling signal to adjust and form a reflecting electromagnetic wave.

Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a device layer having a frontside and a backside; a first interconnect structure disposed on the frontside of the device layer, and having a first seal ring structure; a second interconnect structure disposed on the backside of the device layer; and a diode and a transistor embedded in the device layer, wherein a gate of the transistor is electrically connected to the first seal ring structure by the diode.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.

Abstract: An integrated circuit device includes a transistor, a dielectric layer, a first vertical connecting structure. The transistor includes a gate structure. The dielectric layer surrounds the transistor. The first vertical connecting structure extends through the dielectric layer. The gate contact via is over the gate structure. The front-side metallization pattern is over the transistor. The front-side metallization pattern includes a first conductive path and a dummy conductive pattern. The first conductive path connects the gate contact via to a top end of the first vertical connecting structure. The dummy conductive pattern is connected to the first conductive path. The back-side metallization layer is below the transistor, wherein the back-side metallization layer is connected with a bottom end of the first vertical connecting structure.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a device layer over a device substrate and forming a front-side interconnect structure over the device layer. The method also includes forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure. The method further includes forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide, polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer, and attaching a carrier substrate to the bevel oxide and the oxide layer.

Abstract: Provided are semiconductor dies and methods for forming semiconductor dies. A method includes forming a semiconductor die having under bump metal (UBM) pads in a dense region and in an isolated region; forming external electrical connectors in contact with the UBM pads; and limiting the external electrical connectors to a pre-selected vertical height.

Abstract: A semiconductor structure includes an isolation structure in a substrate, a metal gate structure over the substrate and a portion of the isolation structure, a spacer at sidewalls of the metal gate structure, epitaxial source/drain structure at two sides of the metal gate structure, and a protection layer over the isolation structure. The protection layer and the spacer include a same material.

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

Abstract: The present disclosure discloses a display apparatus having an on-screen display control mechanism. A signal receiving terminal receives a keyboard input signal. A signal transmission circuit receives the keyboard input signal by using an input terminal from the signal receiving terminal and transmits the keyboard input signal to a first output terminal and a second output terminal respectively in a keyboard signal transmission mode and a on-screen display control mode. The display control circuit controls a display panel to display a on-screen display including control items and an indicating object under the on-screen display control mode, receive the keyboard input signal from the second output terminal to retrieve key information and control the indicating object according to the key information to move among the control items to switch a selected control item indicated thereby or execute a control function of the selected control item.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: A Reconfigurable ReflectArray (RRA) structure includes a P-Intrinsic-N (P-I-N) diode and a metal circuit. The metal circuit includes a first metal member and a second metal member. The first metal member is coupled to one end of the P-I-N diode. The second metal member is coupled to another end of the P-I-N diode. One of the first metal member and the second metal member includes a first radiating portion and a second radiating portion. The first radiating portion is located between the P-I-N diode and the second radiating portion. The first radiating portion has a first length. The second radiating portion has a second length. The first length is different from the second length.